[PATCH] drm/amdgpu: Do not skip gfx9.4.3 and sdma4.4.2 fini under SRIOV

[Victor Lu]

GFX and SDMA is not properly deinitialized under SRIOV.

Remove amdgpu_sriov_vf() guards to allow VF to deinitialize correctly.

Signed-off-by: Victor Lu <victorchengchi.lu at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c  | 7 +++++--
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 9 ++++-----
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index b53c8fd4e8cf..fbc34f1797a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2049,7 +2049,6 @@ static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
 		 * hypervisor side.
 		 */
 		WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
-		return;
 	}
 
 	/* Use deinitialize sequence from CAIL when unbinding device
@@ -2068,7 +2067,11 @@ static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
 	}
 
 	gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
-	gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
+
+	/* SRIOV world switch will fail if MEC is disabled */
+	if (!amdgpu_sriov_vf(adev)) {
+		gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
+	}
 }
 
 static int gfx_v9_4_3_hw_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index eaa4f5f49949..fa0752d81c23 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1441,17 +1441,16 @@ static int sdma_v4_4_2_hw_fini(void *handle)
 	uint32_t inst_mask;
 	int i;
 
-	if (amdgpu_sriov_vf(adev))
-		return 0;
-
-	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
+	/* SRIOV does not init RAS features */
+	if ((!amdgpu_sriov_vf(adev)) &&
+            amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
 		for (i = 0; i < adev->sdma.num_instances; i++) {
 			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
 				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
 		}
 	}
 
+	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 
-- 
2.34.1