[PATCH] drm/amd/display: Remove redundant condition in dcn35_calc_blocks_to_gate()
Rodrigo Siqueira Jordao
Rodrigo.Siqueira at amd.com
Mon Mar 18 23:05:09 UTC 2024
On 2/23/24 11:39 PM, Srinivasan Shanmugam wrote:
> pipe_ctx->plane_res.mpcc_inst is of a type that can only hold values
> between 0 and 255, so it's always greater than or equal to 0.
>
> Thus the condition 'pipe_ctx->plane_res.mpcc_inst >= 0' was always true
> and has been removed.
>
> Fixes the below:
> drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn35/dcn35_hwseq.c:1023 dcn35_calc_blocks_to_gate() warn: always true condition '(pipe_ctx->plane_res.mpcc_inst >= 0) => (0-255 >= 0)'
>
> Fixes: 6f8b7565cca4 ("drm/amd/display: Add DCN35 HWSEQ")
> Cc: Qingqing Zhuo <Qingqing.Zhuo at amd.com>
> Cc: Harry Wentland <Harry.Wentland at amd.com>
> Cc: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
> Cc: Roman Li <roman.li at amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai at amd.com>
> Cc: Tom Chung <chiahsuan.chung at amd.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam at amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
> index 4b92df23ff0d..3dbbf6ea2603 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
> @@ -1019,8 +1019,7 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
> if (pipe_ctx->plane_res.dpp)
> update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
>
> - if ((pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp) &&
> - pipe_ctx->plane_res.mpcc_inst >= 0)
> + if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)
> update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
>
> if (pipe_ctx->stream_res.dsc)
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
More information about the amd-gfx
mailing list