[PATCH] drm/amd/amdgpu: add pipe1 hardware support

[Yin, ZhenGuo (Chris)]

[AMD Official Use Only - General]

Hi, Alex

Could you please help to review this patch?
This should fix the bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117.

Thx.

Best,
Zhenguo
Cloud-GPU Core team, SRDC

-----Original Message-----
From: Yin, ZhenGuo (Chris) <ZhenGuo.Yin at amd.com>
Sent: Friday, March 15, 2024 2:12 PM
To: amd-gfx at lists.freedesktop.org
Cc: mdaenzer at redhat.com; Deucher, Alexander <Alexander.Deucher at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Paneer Selvam, Arunpravin <Arunpravin.PaneerSelvam at amd.com>; Deng, Emily <Emily.Deng at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Yin, ZhenGuo (Chris) <ZhenGuo.Yin at amd.com>
Subject: [PATCH] drm/amd/amdgpu: add pipe1 hardware support

Enable pipe1 support starting from SIENNA CICHLID asic.
Need to use correct ref/mask for pipe1 hdp flush.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117
Fixes: 085292c3d780 ("Revert "drm/amd/amdgpu: add pipe1 hardware support"")
Signed-off-by: ZhenGuo Yin <zhenguo.yin at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f90905ef32c7..5eb6f189920b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4518,7 +4518,7 @@ static int gfx_v10_0_sw_init(void *handle)
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                adev->gfx.me.num_me = 1;
-               adev->gfx.me.num_pipe_per_me = 1;
+               adev->gfx.me.num_pipe_per_me = 2;
                adev->gfx.me.num_queue_per_pipe = 1;
                adev->gfx.mec.num_mec = 2;
                adev->gfx.mec.num_pipe_per_mec = 4;
@@ -8317,7 +8317,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
                }
                reg_mem_engine = 0;
        } else {
-               ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
+               ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
                reg_mem_engine = 1; /* pfp */
        }

--
2.35.1