[PATCH v2 2/4] drm/amd/pm: Add PMFW message and capability flags

[Lazar, Lijo]

On 3/28/2024 8:57 AM, Wang, Yang(Kevin) wrote:
> [AMD Official Use Only - General]
> 
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Lijo Lazar
> Sent: Thursday, March 28, 2024 10:36 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Wang, Yang(Kevin) <KevinYang.Wang at amd.com>
> Subject: [PATCH v2 2/4] drm/amd/pm: Add PMFW message and capability flags
> 
> Add flags to categorize messages and PMFW capabilities.
> 
> Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
> ---
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 ++-  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  | 7 +++++++
>  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c        | 2 +-
>  3 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index a870bdd49a4e..aa835df7ba1a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -458,7 +458,7 @@ struct smu_umd_pstate_table {  struct cmn2asic_msg_mapping {
>         int     valid_mapping;
>         int     map_to;
> -       int     valid_in_vf;
> +       uint32_t flags;
>  };
> 
>  struct cmn2asic_mapping {
> @@ -538,6 +538,7 @@ struct smu_context {
>         uint32_t smc_driver_if_version;
>         uint32_t smc_fw_if_version;
>         uint32_t smc_fw_version;
> +       uint32_t smc_fw_caps;
> 
>         bool uploading_custom_pp_table;
>         bool dc_controlled_by_gpio;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> index af427cc7dbb8..c48214e3dc8e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> @@ -445,4 +445,11 @@ enum smu_feature_mask {
>         SMU_FEATURE_COUNT,
>  };
> 
> +/* Message category flags */
> +#define SMU_MSG_VF_FLAG                        (1U << 0)
> +#define SMU_MSG_RAS_PRI                        (1U << 1)
> +
> +/* Firmware capability flags */
> +#define SMU_FW_CAP_RAS_PRI             (1U << 0)
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index b8dbd4e25348..3227e514e8ae 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -437,7 +437,7 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu,
>                         return -EINVAL;
> 
>                 if (amdgpu_sriov_vf(smu->adev) &&
> -                   !msg_mapping.valid_in_vf)
> +                   !(msg_mapping.flags & SMU_MSG_VF_FLAG))
>                         return -EACCES;
> [kevin]:
> 
> Is it possible to use smc_fw_caps uniformly to handle sriov cases (likes FED/ras msg.flags) , which would look more reasonable?
> +       smu->smc_fw_caps |= SMU_FW_CAP_VF ?

Presently, most FW support handling VF messages which is why another
capability is not added.

Messages need to be categorized even if FW capability is there.

Thanks,
Lijo

> 
> Best Regards,
> Kevin
> 
>                 return msg_mapping.map_to;
> --
> 2.25.1
>