[PATCH v9 11/14] drm/amdgpu: fix MES GFX mask

[Alex Deucher]

On Fri, Apr 26, 2024 at 9:57 AM Shashank Sharma <shashank.sharma at amd.com> wrote:
>
> Current MES GFX mask prevents FW to enable oversubscription. This patch
> does the following:
> - Fixes the mask values and adds a description for the same.
> - Removes the central mask setup and makes it IP specific, as it would
>   be different when the number of pipes and queues are different.
>
> V9: introduce this patch in the series
>
> Cc: Christian König <Christian.Koenig at amd.com>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Shashank Sharma <shashank.sharma at amd.com>
> Signed-off-by: Arvind Yadav <arvind.yadav at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 -
>  drivers/gpu/drm/amd/amdgpu/mes_v10_1.c  | 9 +++++++--
>  drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 9 +++++++--
>  4 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index a00cf4756ad0..b405fafc0b71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -151,9 +151,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>                 adev->mes.compute_hqd_mask[i] = 0xc;
>         }
>
> -       for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
> -               adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
> -
>         for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
>                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) <
>                     IP_VERSION(6, 0, 0))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index 4c8fc3117ef8..598556619337 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -110,7 +110,6 @@ struct amdgpu_mes {
>         uint32_t                        vmid_mask_gfxhub;
>         uint32_t                        vmid_mask_mmhub;
>         uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
> -       uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
>         uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
>         uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
>         uint32_t                        sch_ctx_offs;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 1e5ad1e08d2a..4d1121d1a1e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -290,8 +290,13 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)
>                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
>                         mes->compute_hqd_mask[i];
>
> -       for (i = 0; i < MAX_GFX_PIPES; i++)
> -               mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
> +       /*
> +        * GFX pipe 0 queue 0 is being used by kernel
> +        * Set GFX pipe 0 queue 1 for MES scheduling
> +        * GFX pipe 1 can't be used for MES due to HW limitation.
> +        */
> +       mes_set_hw_res_pkt.gfx_hqd_mask[0] = 0x2;
> +       mes_set_hw_res_pkt.gfx_hqd_mask[1] = 0;
>
>         for (i = 0; i < MAX_SDMA_PIPES; i++)
>                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 63f281a9984d..feb7fa2c304c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -387,8 +387,13 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
>                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
>                         mes->compute_hqd_mask[i];
>
> -       for (i = 0; i < MAX_GFX_PIPES; i++)
> -               mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
> +       /*
> +        * GFX pipe 0 queue 0 is being used by kernel
> +        * Set GFX pipe 0 queue 1 for MES scheduling
> +        * GFX pipe 1 can't be used for MES due to HW limitation.
> +        */
> +       mes_set_hw_res_pkt.gfx_hqd_mask[0] = 0x2;
> +       mes_set_hw_res_pkt.gfx_hqd_mask[1] = 0;

FWIW, I think this should work on pipe1.  Might be worth playing with.
The attached patches should enable pipe1 for kernel queues similar to
gfx10.  Anyway, something for the future.
Patch is:
Acked-by: Alex Deucher <alexander.deucher at amd.com>

Alex

>
>         for (i = 0; i < MAX_SDMA_PIPES; i++)
>                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
> --
> 2.43.2
>
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