[PATCH v10 13/14] drm/amdgpu: enable compute/gfx usermode queue

[Christian König]

Am 02.05.24 um 18:31 schrieb Shashank Sharma:
> This patch does the necessary changes required to
> enable compute workload support using the existing
> usermode queues infrastructure.
>
> V9:  Patch introduced
> V10: Add custom IP specific mqd strcuture for compute (Alex)
>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Cc: Christian Koenig <christian.koenig at amd.com>
> Signed-off-by: Arvind Yadav <arvind.yadav at amd.com>
> Signed-off-by: Shashank Sharma <shashank.sharma at amd.com>

Acked-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c    |  3 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c           |  2 ++
>   drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 15 +++++++++++++++
>   include/uapi/drm/amdgpu_drm.h                    | 10 ++++++++++
>   4 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> index f7ece0b31ff9..84bce9434102 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> @@ -189,7 +189,8 @@ amdgpu_userqueue_create(struct drm_file *filp, union drm_amdgpu_userq *args)
>   	int qid, r = 0;
>   
>   	/* Usermode queues are only supported for GFX/SDMA engines as of now */
> -	if (args->in.ip_type != AMDGPU_HW_IP_GFX && args->in.ip_type != AMDGPU_HW_IP_DMA) {
> +	if (args->in.ip_type != AMDGPU_HW_IP_GFX && args->in.ip_type != AMDGPU_HW_IP_DMA
> +			&& args->in.ip_type != AMDGPU_HW_IP_COMPUTE) {
>   		DRM_ERROR("Usermode queue doesn't support IP type %u\n", args->in.ip_type);
>   		return -EINVAL;
>   	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 888edc2b4769..46304d09c4bd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -1349,6 +1349,7 @@ static int gfx_v11_0_sw_init(void *handle)
>   		adev->gfx.mec.num_pipe_per_mec = 4;
>   		adev->gfx.mec.num_queue_per_pipe = 4;
>   		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;
> +		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_v11_0_funcs;
>   		break;
>   	case IP_VERSION(11, 0, 1):
>   	case IP_VERSION(11, 0, 4):
> @@ -1361,6 +1362,7 @@ static int gfx_v11_0_sw_init(void *handle)
>   		adev->gfx.mec.num_pipe_per_mec = 4;
>   		adev->gfx.mec.num_queue_per_pipe = 4;
>   		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;
> +		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_v11_0_funcs;
>   		break;
>   	default:
>   		adev->gfx.me.num_me = 1;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
> index 80375894c4f3..2ae6f720dc66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
> @@ -260,6 +260,21 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,
>   	userq_props->use_doorbell = true;
>   	userq_props->doorbell_index = queue->doorbell_index;
>   
> +	if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) {
> +		struct drm_amdgpu_userq_mqd_compute_gfx_v11 *compute_mqd;
> +
> +		if (mqd_user->mqd_size != sizeof(*compute_mqd)) {
> +			DRM_ERROR("Invalid compute IP MQD size\n");
> +			goto free_mqd_user;
> +		}
> +		compute_mqd = (struct drm_amdgpu_userq_mqd_compute_gfx_v11 *)mqd_user->mqd;
> +
> +		userq_props->eop_gpu_addr = compute_mqd->eop_va;
> +		userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;
> +		userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM;
> +		userq_props->hqd_active = false;
> +	}
> +
>   	queue->userq_prop = userq_props;
>   
>   	r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props);
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 6798139036a1..7ffa9ee885e6 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -429,6 +429,16 @@ struct drm_amdgpu_userq_mqd_gfx_v11 {
>   	__u64   csa_va;
>   };
>   
> +/* GFX V11 Compute IP specific MQD parameters */
> +struct drm_amdgpu_userq_mqd_compute_gfx_v11 {
> +	/**
> +	 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
> +	 * This must be a from a separate GPU object, and must be at least 1 page
> +	 * sized.
> +	 */
> +	__u64   eop_va;
> +};
> +
>   /* vm ioctl */
>   #define AMDGPU_VM_OP_RESERVE_VMID	1
>   #define AMDGPU_VM_OP_UNRESERVE_VMID	2