FW: [PATCH] drm/amdgpu: program device_cntl2 through pci cfg space

[Min, Frank]

[AMD Official Use Only - AMD Internal Distribution Only]

From: Frank Min <Frank.Min at amd.com>

device_cntl2 is accessible from pci config space, so program it through pci cfg space instead of mmio.

Signed-off-by: Frank Min <Frank.Min at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index fe64c04ee20b..5a20bb229788 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -315,6 +315,7 @@ static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev)  static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)  {
        uint32_t def, data;
+       u16 devctl2;

        def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
        data = 0x35EB;
@@ -328,13 +329,15 @@ static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)
        if (def != data)
                WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);

-       def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+       pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2);
+
+       if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN))
+               return;
+
        if (adev->pdev->ltr_path)
-               data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+               pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2,
+PCI_EXP_DEVCTL2_LTR_EN);
        else
-               data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
-       if (def != data)
-               WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+               pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2,
+PCI_EXP_DEVCTL2_LTR_EN);
 }
 #endif

--
2.34.1