[PATCH v1 3/3] drm/amd/amdgpu: Disable MMHUB prefetch for ISP v4.1.1

[Pratap Nirujogi]

Disable MMHUB prefetch for ISP v4.1.1 as a temporary WA until
the GART supports MMHUB TLSi and SAW for ISP HW to access
GART memory using the TLSi path.

Signed-off-by: Pratap Nirujogi <pratap.nirujogi at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c | 12 ++++++++++++
 drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
index 4e17fa03f7b5..67f95f05ecca 100644
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
@@ -104,6 +104,18 @@ static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)
 		goto failure;
 	}
 
+	/*
+	 * Temporary WA added to disable MMHUB TLSi until the GART initialization
+	 * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
+	 * using the TLSi path
+	 */
+	WREG32(mmDAGB1_WRCLI5_V4_1_1 >> 2, 0xFE5FEAA8);
+	WREG32(mmDAGB1_WRCLI9_V4_1_1 >> 2, 0xFE5FEAA8);
+	WREG32(mmDAGB1_WRCLI10_V4_1_1 >> 2, 0xFE5FEAA8);
+	WREG32(mmDAGB1_WRCLI14_V4_1_1 >> 2, 0xFE5FEAA8);
+	WREG32(mmDAGB1_WRCLI19_V4_1_1 >> 2, 0xFE5FEAA8);
+	WREG32(mmDAGB1_WRCLI20_V4_1_1 >> 2, 0xFE5FEAA8);
+
 	return 0;
 
 failure:
diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
index dfb9522c9d6a..6bfb1de191a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
@@ -32,6 +32,13 @@
 
 #include "ivsrcid/isp/irqsrcs_isp_4_1.h"
 
+#define mmDAGB1_WRCLI5_V4_1_1   0x68420
+#define mmDAGB1_WRCLI9_V4_1_1   0x68430
+#define mmDAGB1_WRCLI10_V4_1_1  0x68434
+#define mmDAGB1_WRCLI14_V4_1_1  0x68444
+#define mmDAGB1_WRCLI19_V4_1_1  0x68458
+#define mmDAGB1_WRCLI20_V4_1_1  0x6845C
+
 #define MAX_ISP411_INT_SRC 8
 
 void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp);
-- 
2.34.1