[PATCH 15/32] drm/amd/display: fix YUV video color corruption in DCN401
Zaeem Mohamed
zaeem.mohamed at amd.com
Fri May 31 16:51:28 UTC 2024
From: Samson Tam <samson.tam at amd.com>
[Why]
Missing check causes sequence error which results in chroma
filter coefficients not being updated in certain modes
when we display YUV video in fullscreen. This results in
color corruption in video
[How]
Add back chroma_coef_mode check in dscl_set_scl_filter
so that filter coefficients are calculated and updated when
we have YUV surface
Reviewed-by: Alvin Lee <alvin.lee2 at amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed at amd.com>
Signed-off-by: Samson Tam <samson.tam at amd.com>
---
.../amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
index 6cb3fa4b585c..505929800426 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
@@ -297,17 +297,21 @@ static void dpp401_dscl_set_scl_filter(
if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {
filter_h = scl_data->dscl_prog_data.filter_h;
filter_v = scl_data->dscl_prog_data.filter_v;
- filter_h_c = scl_data->dscl_prog_data.filter_h_c;
- filter_v_c = scl_data->dscl_prog_data.filter_v_c;
+ if (chroma_coef_mode) {
+ filter_h_c = scl_data->dscl_prog_data.filter_h_c;
+ filter_v_c = scl_data->dscl_prog_data.filter_v_c;
+ }
} else {
filter_h = dpp401_dscl_get_filter_coeffs_64p(
scl_data->taps.h_taps, scl_data->ratios.horz);
filter_v = dpp401_dscl_get_filter_coeffs_64p(
scl_data->taps.v_taps, scl_data->ratios.vert);
- filter_h_c = dpp401_dscl_get_filter_coeffs_64p(
- scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
- filter_v_c = dpp401_dscl_get_filter_coeffs_64p(
- scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
+ if (chroma_coef_mode) {
+ filter_h_c = dpp401_dscl_get_filter_coeffs_64p(
+ scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
+ filter_v_c = dpp401_dscl_get_filter_coeffs_64p(
+ scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
+ }
}
h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
--
2.34.1
More information about the amd-gfx
mailing list