[PATCH 29/32] drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35
Zaeem Mohamed
zaeem.mohamed at amd.com
Fri May 31 16:51:42 UTC 2024
From: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
[Why]
3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers
now exist in MCM state.
[How]
Add guards when reading DPP state based on whether the register has a
valid offset.
Reviewed-by: Sung joon Kim <sungjoon.kim at amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed at amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
---
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 29 ++++++++++---------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index f8c0cee34080..7c05fa20078c 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -64,22 +64,23 @@ void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
}
// Shaper LUT (RAM), 3D LUT (mode, bit-depth, size)
- REG_GET(CM_SHAPER_CONTROL,
- CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
- REG_GET(CM_3DLUT_MODE,
- CM_3DLUT_MODE_CURRENT, &s->lut3d_mode);
- REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
- CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
- REG_GET(CM_3DLUT_MODE,
- CM_3DLUT_SIZE, &s->lut3d_size);
+ if (REG(CM_SHAPER_CONTROL))
+ REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
+ if (REG(CM_3DLUT_MODE))
+ REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &s->lut3d_mode);
+ if (REG(CM_3DLUT_READ_WRITE_CONTROL))
+ REG_GET(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
+ if (REG(CM_3DLUT_MODE))
+ REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &s->lut3d_size);
// Blend/Out Gamma (RAM)
- REG_GET(CM_BLNDGAM_CONTROL,
- CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode);
- if (s->rgam_lut_mode){
- REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
- if (!rgam_lut_mode)
- s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
+ if (REG(CM_BLNDGAM_CONTROL)) {
+ REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode);
+ if (s->rgam_lut_mode){
+ REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
+ if (!rgam_lut_mode)
+ s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
+ }
}
}
--
2.34.1
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