[PATCH] drm/amdgpu: Add compatible NPS mode info

[Kamal, Asad]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Asad Kamal <asad.kamal at amd.com>

Thanks & Regards
Asad

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Lijo Lazar
Sent: Wednesday, October 30, 2024 2:00 PM
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Kamal, Asad <Asad.Kamal at amd.com>
Subject: [PATCH] drm/amdgpu: Add compatible NPS mode info

Populate the compatible NPS modes also for providing partition configuration details through sysfs.

Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h    |  1 +
 drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 11 +++++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 7ac89d78a5bf..b63f53242c57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -77,6 +77,7 @@ struct amdgpu_xcp_cfg {
        u8 num_res;
        struct amdgpu_xcp_mgr *xcp_mgr;
        struct kobject kobj;
+       u16 compatible_nps_modes;
 };

 struct amdgpu_xcp_ip_funcs {
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 890976b7ce77..fccccea0d2d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -455,6 +455,7 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
        int max_res[AMDGPU_XCP_RES_MAX] = {};
        bool res_lt_xcp;
        int num_xcp, i;
+       u16 nps_modes;

        if (!(xcp_mgr->supp_xcp_modes & BIT(mode)))
                return -EINVAL;
@@ -467,23 +468,33 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
        switch (mode) {
        case AMDGPU_SPX_PARTITION_MODE:
                num_xcp = 1;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
                break;
        case AMDGPU_DPX_PARTITION_MODE:
                num_xcp = 2;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
                break;
        case AMDGPU_TPX_PARTITION_MODE:
                num_xcp = 3;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
+                           BIT(AMDGPU_NPS4_PARTITION_MODE);
                break;
        case AMDGPU_QPX_PARTITION_MODE:
                num_xcp = 4;
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
+                           BIT(AMDGPU_NPS4_PARTITION_MODE);
                break;
        case AMDGPU_CPX_PARTITION_MODE:
                num_xcp = NUM_XCC(adev->gfx.xcc_mask);
+               nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
+                           BIT(AMDGPU_NPS4_PARTITION_MODE);
                break;
        default:
                return -EINVAL;
        }

+       xcp_cfg->compatible_nps_modes =
+               (adev->gmc.supported_nps_modes & nps_modes);
        xcp_cfg->num_res = ARRAY_SIZE(max_res);

        for (i = 0; i < xcp_cfg->num_res; i++) {
--
2.25.1