[PATCH] drm/amdgpu/pm: add gen5 display to the user on smu v14.0.2/3

[Wang, Yang(Kevin)]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Yang Wang <kevinyang.wang at amd.com>

Best Regards,
Kevin

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Kenneth Feng
Sent: Tuesday, November 19, 2024 11:13
To: amd-gfx at lists.freedesktop.org
Cc: Wang, Yang(Kevin) <KevinYang.Wang at amd.com>; Feng, Kenneth <Kenneth.Feng at amd.com>
Subject: [PATCH] drm/amdgpu/pm: add gen5 display to the user on smu v14.0.2/3

add gen5 display to the user on smu v14.0.2/3

Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c            | 8 ++++++--
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h         | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c       | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 6 ++++--
 4 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index c3a6b6f20455..5cba64996cdb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1714,7 +1714,9 @@ static int smu_smc_hw_setup(struct smu_context *smu)
                return ret;
        }

-       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5)
+               pcie_gen = 4;
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
                pcie_gen = 3;
        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
                pcie_gen = 2;
@@ -1727,7 +1729,9 @@ static int smu_smc_hw_setup(struct smu_context *smu)
         * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
         * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
         */
-       if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+       if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
+               pcie_width = 7;
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
                pcie_width = 6;
        else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
                pcie_width = 5;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 0546b02e198d..29a4583db873 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -53,7 +53,7 @@
 #define CTF_OFFSET_MEM                 5

 extern const int decoded_link_speed[5]; -extern const int decoded_link_width[7];
+extern const int decoded_link_width[8];

 #define DECODE_GEN_SPEED(gen_speed_idx)                (decoded_link_speed[gen_speed_idx])
 #define DECODE_LANE_WIDTH(lane_width_idx)      (decoded_link_width[lane_width_idx])
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 5460f8e62264..4d083f7f772e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -49,7 +49,7 @@
 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX   0

 const int decoded_link_speed[5] = {1, 2, 3, 4, 5}; -const int decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
+const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32};
 /*
  * DO NOT use these for err/warn/info/debug messages.
  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index 59b369eff30f..5e2629219280 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -1173,13 +1173,15 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu,
                                        (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
                                        (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
                                        (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
-                                       (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
+                                       (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," :
+                                       (pcie_table->pcie_gen[i] == 4) ? "32.0GT/s," : "",
                                        (pcie_table->pcie_lane[i] == 1) ? "x1" :
                                        (pcie_table->pcie_lane[i] == 2) ? "x2" :
                                        (pcie_table->pcie_lane[i] == 3) ? "x4" :
                                        (pcie_table->pcie_lane[i] == 4) ? "x8" :
                                        (pcie_table->pcie_lane[i] == 5) ? "x12" :
-                                       (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
+                                       (pcie_table->pcie_lane[i] == 6) ? "x16" :
+                                       (pcie_table->pcie_lane[i] == 7) ? "x32" : "",
                                        pcie_table->clk_freq[i],
                                        (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
                                        (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
--
2.34.1