[PATCH 2/3] drm/amdgpu: Add mqd support for userq compute queue

[Arunpravin Paneer Selvam]

Add mqd support for userq compute queue.

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 13 ++++++++++---
 drivers/gpu/drm/amd/include/v11_structs.h        |  4 ++--
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
index fe4efe5ba6ac..3d9be36a9f0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
@@ -232,10 +232,17 @@ static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
 
 static void mes_v11_0_userq_set_fence_space(struct amdgpu_usermode_queue *queue)
 {
-	struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
+	if (queue->queue_type == AMDGPU_HW_IP_GFX) {
+		struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
+
+		mqd->fenceaddress_lo = lower_32_bits(queue->fence_drv->gpu_addr);
+		mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr);
+	} else if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) {
+		struct v11_compute_mqd *mqd = queue->mqd.cpu_ptr;
 
-	mqd->fenceaddress_lo = lower_32_bits(queue->fence_drv->gpu_addr);
-	mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr);
+		mqd->fenceaddress_lo = lower_32_bits(queue->fence_drv->gpu_addr);
+		mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr);
+	}
 }
 
 static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,
diff --git a/drivers/gpu/drm/amd/include/v11_structs.h b/drivers/gpu/drm/amd/include/v11_structs.h
index 797ce6a1e56e..beef3d203f3c 100644
--- a/drivers/gpu/drm/amd/include/v11_structs.h
+++ b/drivers/gpu/drm/amd/include/v11_structs.h
@@ -1118,8 +1118,8 @@ struct v11_compute_mqd {
 	uint32_t reserved_443; // offset: 443  (0x1BB)
 	uint32_t reserved_444; // offset: 444  (0x1BC)
 	uint32_t reserved_445; // offset: 445  (0x1BD)
-	uint32_t reserved_446; // offset: 446  (0x1BE)
-	uint32_t reserved_447; // offset: 447  (0x1BF)
+	uint32_t fenceaddress_lo; // offset: 446  (0x1BE)
+	uint32_t fenceaddress_hi; // offset: 447  (0x1BF)
 	uint32_t gws_0_val; // offset: 448  (0x1C0)
 	uint32_t gws_1_val; // offset: 449  (0x1C1)
 	uint32_t gws_2_val; // offset: 450  (0x1C2)
-- 
2.25.1