[PATCH 4/9] drm/amdgpu/sdma6: update mqd init for UQ

[Alex Deucher]

On Thu, Nov 21, 2024 at 8:42 AM Shashank Sharma <shashank.sharma at amd.com> wrote:
>
> From: Alex Deucher <alexander.deucher at amd.com>
>
> Set the addresses for the UQ metadata.
>
> V2: Fix lower address mask (Shashank)
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Shashank Sharma <shashank.sharma at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index 6e9fa0bc89cd..9af6aeeca063 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -891,6 +891,9 @@ static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
>         m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
>         m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
>
> +       m->sdmax_rlcx_csa_addr_lo = prop->csa_addr & 0xFFFFFFFC;

I think lower_32_bits is cleaner.  Plus, if the address is not aligned
properly, masking it here won't help.  The hw ignores the lower bits
anyway.

Alex

> +       m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr);
> +
>         return 0;
>  }
>
> --
> 2.46.2
>