[PATCH 2/6] drm/amdgpu/gfx10: Apply Isolation Enforcement to GFX & Compute rings

Alex Deucher alexdeucher at gmail.com
Wed Oct 2 16:41:58 UTC 2024


On Wed, Oct 2, 2024 at 12:58 AM Srinivasan Shanmugam
<srinivasan.shanmugam at amd.com> wrote:
>
> This commit applies isolation enforcement to the GFX and Compute rings
> in the gfx_v10_0 module.
>
> The commit sets `amdgpu_gfx_enforce_isolation_ring_begin_use` and
> `amdgpu_gfx_enforce_isolation_ring_end_use` as the functions to be
> called when a ring begins and ends its use, respectively.
>
> `amdgpu_gfx_enforce_isolation_ring_begin_use` is called when a ring
> begins its use. This function cancels any scheduled
> `enforce_isolation_work` and, if necessary, signals the Kernel Fusion
> Driver (KFD) to stop the runqueue.
>
> `amdgpu_gfx_enforce_isolation_ring_end_use` is called when a ring ends
> its use. This function schedules `enforce_isolation_work` to be run
> after a delay.
>
> These functions are part of the Enforce Isolation Handler, which
> enforces shader isolation on AMD GPUs to prevent data leakage between
> different processes.
>
> Cc: Christian König <christian.koenig at amd.com>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 2b230971c58a..57f28cb40913 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9802,6 +9802,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
>         .reset = gfx_v10_0_reset_kgq,
>         .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
> +       .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
> +       .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
>  };
>
>  static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
> @@ -9841,6 +9843,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
>         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
>         .reset = gfx_v10_0_reset_kcq,
>         .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
> +       .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
> +       .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
>  };
>
>  static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
> --
> 2.34.1
>


More information about the amd-gfx mailing list