[PATCH] drm/amd/display: fix hibernate entry for DCN35+

[Alex Deucher]

On Fri, Oct 4, 2024 at 4:43 PM Hamza Mahfooz <hamza.mahfooz at amd.com> wrote:
>
> Since, two suspend-resume cycles are required to enter hibernate and,
> since we only need to enable idle optimizations in the first cycle
> (which is pretty much equivalent to s2idle). We can check in_s0ix, to
> prevent the system from entering idle optimizations before it actually
> enters hibernate (from display's perspective).
>
> Cc: stable at vger.kernel.org # 6.10+
> Signed-off-by: Hamza Mahfooz <hamza.mahfooz at amd.com>
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 4651b884d8d9..546a168a2fbf 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2996,10 +2996,11 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
>
>         hpd_rx_irq_work_suspend(dm);
>
> -       if (adev->dm.dc->caps.ips_support)
> -               dc_allow_idle_optimizations(adev->dm.dc, true);
> -
>         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
> +
> +       if (dm->dc->caps.ips_support && adev->in_s0ix)
> +               dc_allow_idle_optimizations(dm->dc, true);
> +

Is the ordering change with respect to dc_set_power_state() intended?

Alex

>         dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
>
>         return 0;
> --
> 2.46.0
>