[PATCH] drm/amdgpu: Increase MES log buffer to dump mes scratch data

Xu, Feifei feifxu at amd.com
Sat Oct 12 02:23:32 UTC 2024


Acked-by: Feifei Xu <Feifei Xu at amd.com>

On 10/11/2024 12:10 AM, shaoyunl wrote:
> MES internal scratch data is useful for mes debug, it can only located
> in VRAM, change the allocation type and increase size for mes 11
>
> Signed-off-by: shaoyunl<shaoyun.liu at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 12 +++++++++++-
>   3 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 83d0f731fb65..bf584e9bcce4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -104,7 +104,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
>   		return 0;
>   
>   	r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE,
> -				    AMDGPU_GEM_DOMAIN_GTT,
> +				    AMDGPU_GEM_DOMAIN_VRAM,
>   				    &adev->mes.event_log_gpu_obj,
>   				    &adev->mes.event_log_gpu_addr,
>   				    &adev->mes.event_log_cpu_addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index 45e3508f0f8e..79f13d7e5e16 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -40,6 +40,7 @@
>   #define AMDGPU_MES_VERSION_MASK		0x00000fff
>   #define AMDGPU_MES_API_VERSION_MASK	0x00fff000
>   #define AMDGPU_MES_FEAT_VERSION_MASK	0xff000000
> +#define AMDGPU_MES_MSCRATCH_SIZE	0x8000
>   
>   enum amdgpu_mes_priority_level {
>   	AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 03bf865fbdd4..aa2e9ef4ff12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -913,6 +913,16 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
>   	uint32_t pipe, data = 0;
>   
>   	if (enable) {
> +		if (amdgpu_mes_log_enable) {
> +			WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
> +				lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
> +			WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
> +				upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
> +			dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
> +				RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
> +				RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
> +		}
> +
>   		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
>   		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
>   		data = REG_SET_FIELD(data, CP_MES_CNTL,
> @@ -1375,7 +1385,7 @@ static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
>   	adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
>   	adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
>   
> -	adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
> +	adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
>   
>   	r = amdgpu_mes_init(adev);
>   	if (r)
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