[PATCH] drm/amdgpu: set MES GFX HQD mask

Sharma, Shashank shashank.sharma at amd.com
Tue Oct 15 16:53:14 UTC 2024


On 15/10/2024 18:50, Alex Deucher wrote:
> On Tue, Oct 15, 2024 at 12:33 PM Shashank Sharma
> <shashank.sharma at amd.com> wrote:
>> This patch sets MES HQD mask to setup GFX queues for MES and KIQ
>> operations. We are using one queue each for KIQ operations, and
>> setting rest of the queues for MES scheduling.
>>
>> This also fixes a regression for missing Navi 4x MES mask from
>> usermode queue series.
>>
>> V2: Rebase on staging, accommodate existing changes on Navi 3X
>>
>> Fixes: 1d316a52498f ("drm/amdgpu: fix MES GFX mask")
>> Cc: Alex Deucher <alexander.deucher at amd.com>
>> Cc: Christian König <Christian.Koenig at amd.com>
>> Cc: Arvind Yadav <arvind.yadav at amd.com>
>> Signed-off-by: Shashank Sharma <shashank.sharma at amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 20 +++++++++++++-------
>>   drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 15 ++++++++++++---
>>   2 files changed, 25 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>> index 03bf865fbdd4..1f8ce64a5bff 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>> @@ -654,6 +654,18 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
>>                          offsetof(union MESAPI__MISC, api_status));
>>   }
>>
>> +static void mes_v11_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
>> +{
>> +       /*
>> +        * GFX pipe 0 queue 0 is being used by KIQ
> Minor nit, pipe 0 queue 0 is the kernel gfx queue.  KIQ is in the MEC
> and managed by MES on gfx11+.
Ah, my bad, noted.
>
>> +        * Set GFX pipe 0 queue 1 for MES scheduling
>> +        * mask = 10b
>> +        * GFX pipe 1 can't be used for MES due to HW limitation.
>> +        */
>> +       pkt->gfx_hqd_mask[0] = 0x2;
>> +       pkt->gfx_hqd_mask[1] = 0;
>> +}
>> +
>>   static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
>>   {
>>          int i;
>> @@ -678,13 +690,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
>>                  mes_set_hw_res_pkt.compute_hqd_mask[i] =
>>                          mes->compute_hqd_mask[i];
>>
>> -       /*
>> -        * GFX pipe 0 queue 0 is being used by kernel
>> -        * Set GFX pipe 0 queue 1 for MES scheduling
>> -        * GFX pipe 1 can't be used for MES due to HW limitation.
>> -        */
>> -       mes_set_hw_res_pkt.gfx_hqd_mask[0] = 0x2;
>> -       mes_set_hw_res_pkt.gfx_hqd_mask[1] = 0;
>> +       mes_v11_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
>>
>>          for (i = 0; i < MAX_SDMA_PIPES; i++)
>>                  mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>> index 3daa8862e622..78aad9c4ddbc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>> @@ -557,6 +557,17 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
>>                          offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
>>   }
>>
>> +static void mes_v12_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
>> +{
>> +       /*
>> +        * GFX V12 has only one GFX pipe, but 8 queues in it.
>> +        * GFX pipe 0 queue 0 is being used by KIQ.
> Same comment here.

Noted

- Shashank

> With those addressed, the patch is:
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
>> +        * Set GFX pipe 0 queue 1-7 for MES scheduling
>> +        * mask = 1111 1110b
>> +        */
>> +       pkt->gfx_hqd_mask[0] = 0xFE;
>> +}
>> +
>>   static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
>>   {
>>          int i;
>> @@ -579,9 +590,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
>>                          mes_set_hw_res_pkt.compute_hqd_mask[i] =
>>                                  mes->compute_hqd_mask[i];
>>
>> -               for (i = 0; i < MAX_GFX_PIPES; i++)
>> -                       mes_set_hw_res_pkt.gfx_hqd_mask[i] =
>> -                               mes->gfx_hqd_mask[i];
>> +               mes_v12_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
>>
>>                  for (i = 0; i < MAX_SDMA_PIPES; i++)
>>                          mes_set_hw_res_pkt.sdma_hqd_mask[i] =
>> --
>> 2.46.2
>>


More information about the amd-gfx mailing list