[PATCH] drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih

[Alex Deucher]

On Tue, Oct 15, 2024 at 2:23 PM Victor Lu <victorchengchi.lu at amd.com> wrote:
>
> Port this change to vega20_ih.c:
> "89ae318001e5 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts"

Might be helpful to quote the commit message here just so it's clear
why that change is needed.  With that, the patch is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

>
> Signed-off-by: Victor Lu <victorchengchi.lu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 27 ++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> index a42404a58015..a71552ffe0f0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> @@ -114,6 +114,33 @@ static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
>         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
>         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
>
> +       if (enable) {
> +               /* Unset the CLEAR_OVERFLOW bit to make sure the next step
> +                * is switching the bit from 0 to 1
> +                */
> +               tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +               if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> +                       if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
> +                               return -ETIMEDOUT;
> +               } else {
> +                       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +               }
> +
> +               /* Clear RB_OVERFLOW bit */
> +               tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> +               if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> +                       if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
> +                               return -ETIMEDOUT;
> +               } else {
> +                       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +               }
> +
> +               /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +                * can be detected.
> +                */
> +               tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +       }
> +
>         /* enable_intr field is only valid in ring0 */
>         if (ih == &adev->irq.ih)
>                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
> --
> 2.34.1
>