[PATCH 07/10] drm/amdgpu: Drop delayed reset work handler
Alex Deucher
alexdeucher at gmail.com
Mon Sep 9 21:36:41 UTC 2024
On Mon, Sep 2, 2024 at 3:34 AM Lijo Lazar <lijo.lazar at amd.com> wrote:
>
> Drop delayed reset work handler as it is no longer used.
>
> Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 80 -------------------------
> 2 files changed, 84 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index d17506d9adae..9285108d537f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -131,10 +131,6 @@ struct amdgpu_mgpu_info {
> uint32_t num_gpu;
> uint32_t num_dgpu;
> uint32_t num_apu;
> -
> - /* delayed reset_func for XGMI configuration if necessary */
> - struct delayed_work delayed_reset_work;
> - bool pending_reset;
> };
>
> enum amdgpu_ss {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 3dece2e69608..4f644b120df7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -221,8 +221,6 @@ int amdgpu_wbrf = -1;
> int amdgpu_damage_clips = -1; /* auto */
> int amdgpu_umsch_mm_fwlog;
>
> -static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
> -
> DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
> "DRM_UT_CORE",
> "DRM_UT_DRIVER",
> @@ -237,9 +235,6 @@ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
>
> struct amdgpu_mgpu_info mgpu_info = {
> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> - .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
> - mgpu_info.delayed_reset_work,
> - amdgpu_drv_delayed_reset_work_handler, 0),
> };
> int amdgpu_ras_enable = -1;
> uint amdgpu_ras_mask = 0xffffffff;
> @@ -2455,81 +2450,6 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
> adev->mp1_state = PP_MP1_STATE_NONE;
> }
>
> -/**
> - * amdgpu_drv_delayed_reset_work_handler - work handler for reset
> - *
> - * @work: work_struct.
> - */
> -static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
> -{
> - struct list_head device_list;
> - struct amdgpu_device *adev;
> - int i, r;
> - struct amdgpu_reset_context reset_context;
> -
> - memset(&reset_context, 0, sizeof(reset_context));
> -
> - mutex_lock(&mgpu_info.mutex);
> - if (mgpu_info.pending_reset == true) {
> - mutex_unlock(&mgpu_info.mutex);
> - return;
> - }
> - mgpu_info.pending_reset = true;
> - mutex_unlock(&mgpu_info.mutex);
> -
> - /* Use a common context, just need to make sure full reset is done */
> - reset_context.method = AMD_RESET_METHOD_NONE;
> - set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
> -
> - for (i = 0; i < mgpu_info.num_dgpu; i++) {
> - adev = mgpu_info.gpu_ins[i].adev;
> - reset_context.reset_req_dev = adev;
> - r = amdgpu_device_pre_asic_reset(adev, &reset_context);
> - if (r) {
> - dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
> - r, adev_to_drm(adev)->unique);
> - }
> - if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
> - r = -EALREADY;
> - }
> - for (i = 0; i < mgpu_info.num_dgpu; i++) {
> - adev = mgpu_info.gpu_ins[i].adev;
> - flush_work(&adev->xgmi_reset_work);
> - }
> -
> - /* reset function will rebuild the xgmi hive info , clear it now */
> - for (i = 0; i < mgpu_info.num_dgpu; i++)
> - amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
> -
> - INIT_LIST_HEAD(&device_list);
> -
> - for (i = 0; i < mgpu_info.num_dgpu; i++)
> - list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
> -
> - /* unregister the GPU first, reset function will add them back */
> - list_for_each_entry(adev, &device_list, reset_list)
> - amdgpu_unregister_gpu_instance(adev);
> -
> - /* Use a common context, just need to make sure full reset is done */
> - set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
> - set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);
> - r = amdgpu_do_asic_reset(&device_list, &reset_context);
> -
> - if (r) {
> - DRM_ERROR("reinit gpus failure");
> - return;
> - }
> - for (i = 0; i < mgpu_info.num_dgpu; i++) {
> - adev = mgpu_info.gpu_ins[i].adev;
> - if (!adev->kfd.init_complete) {
> - kgd2kfd_init_zone_device(adev);
> - amdgpu_amdkfd_device_init(adev);
> - amdgpu_amdkfd_drm_client_create(adev);
> - }
> - amdgpu_ttm_set_buffer_funcs_status(adev, true);
> - }
> -}
> -
> static int amdgpu_pmops_prepare(struct device *dev)
> {
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> --
> 2.25.1
>
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