[PATCH] drm/amdgpu/gfx9.4.3: set additional bits on MEC halt

[Amber Lin]

Tested-by: Amber Lin <Amber.Lin at amd.com>
Reviewed-by: Amber Lin <Amber.Lin at amd.com>

Regards,
Amber

On 9/12/24 15:24, Alex Deucher wrote:
> Need to set the pipe reset and cache invalidation bits
> on halt otherwise we can get stale state if the CP firmware
> changes (e.g., on module unload and reload).
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 1cc748aaff3b..b865281b4132 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -1703,7 +1703,15 @@ static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
>   		dev_info(adev->dev, "GRBM_STATUS=0x%08X on unhalt\n", tmp);
>   	} else {
>   		WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
> -			(CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
> +			(CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK |
> +			 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK |
> +			 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK |
> +			 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK |
> +			 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK |
> +			 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK |
> +			 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK |
> +			 CP_MEC_CNTL__MEC_ME1_HALT_MASK |
> +			 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
>   		adev->gfx.kiq[xcc_id].ring.sched.ready = false;
>   		dev_info(adev->dev, "GRBM_STATUS=0x%08X on halt\n", tmp);
>   	}