[PATCH] AMDGPU: init saw registers for mmhub v1.0

[Alex Deucher]

On Thu, Sep 12, 2024 at 9:40 PM Zhu Lingshan <lingshan.zhu at amd.com> wrote:
>
> This commits init registers in the Stand Along Walker
> for mmhub v1.0, to support ISP use cases.
>
> Signed-off-by: Zhu Lingshan <lingshan.zhu at amd.com>
> Reported-and-Tested-by: Du Bin <bin.du at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       | 48 +++++++++++++++++++
>  .../include/asic_reg/mmhub/mmhub_1_0_offset.h | 23 +++++++++
>  2 files changed, 71 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index e3ddd22aa172..80864898b480 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -229,6 +229,52 @@ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
>                      0);
>  }
>
> +static void mmhub_v1_0_init_saw(struct amdgpu_device *adev)
> +{
> +       uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
> +       uint32_t tmp;
> +
> +       /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 */
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
> +                           lower_32_bits(pt_base >> 12));
> +
> +       /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 */
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
> +                           upper_32_bits(pt_base >> 12));
> +
> +       /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 */
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
> +                           (u32)(adev->gmc.gart_start >> 12));
> +
> +       /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 */
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
> +                           (u32)(adev->gmc.gart_start >> 44));
> +
> +       /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 */
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
> +                           (u32)(adev->gmc.gart_end >> 12));
> +
> +       /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 */
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
> +                           (u32)(adev->gmc.gart_end >> 44));
> +
> +       /* Program SAW CONTEXT0 CNTL */
> +       tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL);
> +       tmp |= 1 << CONTEXT0_CNTL_ENABLE_OFFSET;
> +       tmp &= ~(3 << CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET);
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL, tmp);
> +
> +       /* Disable all Contexts except Context0 */
> +       tmp = 0xfffe;
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXTS_DISABLE, tmp);
> +
> +       /* Program SAW CNTL4 */
> +       tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4);
> +       tmp |= 1 << VMC_TAP_PDE_REQUEST_SNOOP_OFFSET;
> +       tmp |= 1 << VMC_TAP_PTE_REQUEST_SNOOP_OFFSET;
> +       WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4, tmp);
> +}
> +
>  static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
>  {
>         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
> @@ -283,6 +329,8 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
>                                     i * hub->ctx_addr_distance,
>                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
>         }
> +
> +       mmhub_v1_0_init_saw(adev);

Do these exist on all mmhub v1 based chips or just some specific ones?
 I.e., is there any problem programming these for all chips that use
mmhub v1?

Alex

>  }
>
>  static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
> index 2c3ce243861a..380e44230bda 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
> @@ -1232,6 +1232,29 @@
>  #define mmMC_VM_MX_L1_PERFCOUNTER_HI                                                                   0x059d
>  #define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX                                                          0
>
> +// Stand Alone Walker Registers
> +#define VMC_TAP_PDE_REQUEST_SNOOP_OFFSET                                                               8
> +#define VMC_TAP_PTE_REQUEST_SNOOP_OFFSET                                                               11
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                 0x0606
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                        0
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                 0x0607
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                        0
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                0x0608
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                       0
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                0x0609
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                       0
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                  0x060a
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                         0
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                  0x060b
> +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                         0
> +#define mmVM_L2_SAW_CONTEXT0_CNTL                                                                      0x0604
> +#define mmVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX                                                             0
> +#define CONTEXT0_CNTL_ENABLE_OFFSET                                                                    0
> +#define CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET                                                          1
> +#define mmVM_L2_SAW_CONTEXTS_DISABLE                                                                   0x060c
> +#define mmVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX                                                          0
> +#define mmVM_L2_SAW_CNTL4                                                                              0x0603
> +#define mmVM_L2_SAW_CNTL4_BASE_IDX                                                                     0
>
>  // addressBlock: mmhub_utcl2_atcl2dec
>  // base address: 0x69900
> --
> 2.43.5
>