[PATCH 13/21] drm/amd/display: correct register Clock Gater incorrectly disabled

[Aurabindo Pillai]

From: Charlene Liu <Charlene.Liu at amd.com>

[why]
The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater
when the DPP is enabled.

The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode.
This will disable the clock gater and the DPPCLK register clock branch will always be running.
As a consequence, the dynamic power will be higher than expected.

Reviewed-by: Alvin Lee <alvin.lee2 at amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu at amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
index 8473c694bfdc..9f885a03eec6 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
@@ -50,13 +50,11 @@ void dpp35_dppclk_control(
 				DPPCLK_RATE_CONTROL, dppclk_div,
 				DPP_CLOCK_ENABLE, 1);
 		else
-			REG_UPDATE_2(DPP_CONTROL,
-					DPP_CLOCK_ENABLE, 1,
-					DISPCLK_R_GATE_DISABLE, 1);
+			REG_UPDATE(DPP_CONTROL,
+					DPP_CLOCK_ENABLE, 1);
 	} else
-		REG_UPDATE_2(DPP_CONTROL,
-				DPP_CLOCK_ENABLE, 0,
-				DISPCLK_R_GATE_DISABLE, 0);
+		REG_UPDATE(DPP_CONTROL,
+				DPP_CLOCK_ENABLE, 0);
 }
 
 void dpp35_program_bias_and_scale_fcnv(
-- 
2.46.0