[v5 2/6] drm/amdgpu: Register the new sdma function pointers for each sdma IP version that needs them
Alex Deucher
alexdeucher at gmail.com
Fri Apr 11 15:51:35 UTC 2025
On Fri, Apr 11, 2025 at 4:37 AM Jesse.zhang at amd.com <jesse.zhang at amd.com> wrote:
>
> From: "Jesse.zhang at amd.com" <Jesse.zhang at amd.com>
>
> Register stop/start/soft_reset queue functions for SDMA IP versions
> v4.4.2, v5.0 and v5.2.
>
> Suggested-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Jesse Zhang <jesse.zhang at amd.com>
Might want to split this per IP? Either way:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 22 +++---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 76 ++++++++++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 92 ++++++++++++++----------
> 3 files changed, 125 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index 688a720bbbbd..c663c63485f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -108,6 +108,8 @@ static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
> static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
> static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev);
> static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev);
> +static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring);
> +static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring);
>
> static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
> u32 instance, u32 offset)
> @@ -1333,6 +1335,11 @@ static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
> }
> }
>
> +static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = {
> + .stop_kernel_queue = &sdma_v4_4_2_stop_queue,
> + .start_kernel_queue = &sdma_v4_4_2_restore_queue,
> +};
> +
> static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> @@ -1352,7 +1359,6 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
> sdma_v4_4_2_set_irq_funcs(adev);
> sdma_v4_4_2_set_ras_funcs(adev);
> sdma_v4_4_2_set_engine_reset_funcs(adev);
> -
> return 0;
> }
>
> @@ -1447,6 +1453,7 @@ static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block)
> /* Initialize guilty flags for GFX and PAGE queues */
> adev->sdma.instance[i].gfx_guilty = false;
> adev->sdma.instance[i].page_guilty = false;
> + adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs;
>
> ring = &adev->sdma.instance[i].ring;
> ring->ring_obj = NULL;
> @@ -1678,11 +1685,12 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
> return r;
> }
>
> -static int sdma_v4_4_2_stop_queue(struct amdgpu_device *adev, uint32_t instance_id)
> +static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
> {
> + struct amdgpu_device *adev = ring->adev;
> + u32 instance_id = GET_INST(SDMA0, ring->me);
> u32 inst_mask;
> uint64_t rptr;
> - struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring;
>
> if (amdgpu_sriov_vf(adev))
> return -EINVAL;
> @@ -1715,11 +1723,11 @@ static int sdma_v4_4_2_stop_queue(struct amdgpu_device *adev, uint32_t instance_
> return 0;
> }
>
> -static int sdma_v4_4_2_restore_queue(struct amdgpu_device *adev, uint32_t instance_id)
> +static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)
> {
> - int i;
> + struct amdgpu_device *adev = ring->adev;
> u32 inst_mask;
> - struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring;
> + int i;
>
> inst_mask = 1 << ring->me;
> udelay(50);
> @@ -1740,8 +1748,6 @@ static int sdma_v4_4_2_restore_queue(struct amdgpu_device *adev, uint32_t instan
> }
>
> static struct sdma_on_reset_funcs sdma_v4_4_2_engine_reset_funcs = {
> - .pre_reset = sdma_v4_4_2_stop_queue,
> - .post_reset = sdma_v4_4_2_restore_queue,
> };
>
> static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index e1348b6d9c6a..bef80b318f8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -112,6 +112,8 @@ static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
> static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
> static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
> static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
> +static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring);
> +static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring);
>
> static const struct soc15_reg_golden golden_settings_sdma_5[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
> @@ -1323,6 +1325,36 @@ static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
> }
>
> +static int sdma_v5_0_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)
> +{
> + u32 grbm_soft_reset;
> + u32 tmp;
> +
> + grbm_soft_reset = REG_SET_FIELD(0,
> + GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
> + 1);
> + grbm_soft_reset <<= instance_id;
> +
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> + tmp |= grbm_soft_reset;
> + DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
> + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> +
> + udelay(50);
> +
> + tmp &= ~grbm_soft_reset;
> + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> + return 0;
> +}
> +
> +static const struct amdgpu_sdma_funcs sdma_v5_0_sdma_funcs = {
> + .stop_kernel_queue = &sdma_v5_0_stop_queue,
> + .start_kernel_queue = &sdma_v5_0_restore_queue,
> + .soft_reset_kernel_queue = &sdma_v5_0_soft_reset_engine,
> +};
> +
> static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> @@ -1365,6 +1397,7 @@ static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block)
> return r;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> + adev->sdma.instance[i].funcs = &sdma_v5_0_sdma_funcs;
> ring = &adev->sdma.instance[i].ring;
> ring->ring_obj = NULL;
> ring->use_doorbell = true;
> @@ -1505,9 +1538,17 @@ static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)
>
> static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
> {
> + struct amdgpu_device *adev = ring->adev;
> + u32 inst_id = ring->me;
> +
> + return amdgpu_sdma_reset_engine(adev, inst_id);
> +}
> +
> +static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring)
> +{
> + u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, stat1_reg;
> struct amdgpu_device *adev = ring->adev;
> int i, j, r;
> - u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg;
>
> if (amdgpu_sriov_vf(adev))
> return -EINVAL;
> @@ -1562,30 +1603,25 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
> cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
> cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);
> WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);
> +err0:
> + amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> + return r;
> +}
>
> - /* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */
> - preempt = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT));
> - preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0);
> - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt);
> -
> - soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> - soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i;
> -
> - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset);
> -
> - udelay(50);
> -
> - soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i);
> - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset);
> +static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + u32 inst_id = ring->me;
> + u32 freeze;
> + int r;
>
> + amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> /* unfreeze*/
> - freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));
> + freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));
> freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
> - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);
> + WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
>
> - r = sdma_v5_0_gfx_resume_instance(adev, i, true);
> -
> -err0:
> + r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 964f12afac9e..4cd7010ad0d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -113,6 +113,8 @@ static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
> static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
> static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
> static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
> +static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring);
> +static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring);
>
> static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
> {
> @@ -759,37 +761,49 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
> return 0;
> }
>
> -static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block)
> +static int sdma_v5_2_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)
> {
> - struct amdgpu_device *adev = ip_block->adev;
> u32 grbm_soft_reset;
> u32 tmp;
> - int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - grbm_soft_reset = REG_SET_FIELD(0,
> - GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
> - 1);
> - grbm_soft_reset <<= i;
> + grbm_soft_reset = REG_SET_FIELD(0,
> + GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
> + 1);
> + grbm_soft_reset <<= instance_id;
>
> - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> - tmp |= grbm_soft_reset;
> - DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
> - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> + tmp |= grbm_soft_reset;
> + DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
> + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
>
> - udelay(50);
> + udelay(50);
>
> - tmp &= ~grbm_soft_reset;
> - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
> - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> + tmp &= ~grbm_soft_reset;
> + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> + return 0;
> +}
>
> +static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block)
> +{
> + struct amdgpu_device *adev = ip_block->adev;
> + int i;
> +
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + sdma_v5_2_soft_reset_engine(adev, i);
> udelay(50);
> }
>
> return 0;
> }
>
> +static const struct amdgpu_sdma_funcs sdma_v5_2_sdma_funcs = {
> + .stop_kernel_queue = &sdma_v5_2_stop_queue,
> + .start_kernel_queue = &sdma_v5_2_restore_queue,
> + .soft_reset_kernel_queue = &sdma_v5_2_soft_reset_engine,
> +};
> +
> /**
> * sdma_v5_2_start - setup and start the async dma engines
> *
> @@ -1302,6 +1316,7 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block)
> }
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> + adev->sdma.instance[i].funcs = &sdma_v5_2_sdma_funcs;
> ring = &adev->sdma.instance[i].ring;
> ring->ring_obj = NULL;
> ring->use_doorbell = true;
> @@ -1435,10 +1450,18 @@ static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
> }
>
> static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + u32 inst_id = ring->me;
> +
> + return amdgpu_sdma_reset_engine(adev, inst_id);
> +}
> +
> +static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> int i, j, r;
> - u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg;
> + u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, stat1_reg;
>
> if (amdgpu_sriov_vf(adev))
> return -EINVAL;
> @@ -1495,31 +1518,26 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
> cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);
> WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);
>
> - /* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */
> - preempt = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT));
> - preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0);
> - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt);
> -
> - soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
> - soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i;
> -
> -
> - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset);
> -
> - udelay(50);
> -
> - soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i);
> +err0:
> + amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> + return r;
> +}
>
> - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset);
> +static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + u32 inst_id = ring->me;
> + u32 freeze;
> + int r;
>
> + amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> /* unfreeze and unhalt */
> - freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));
> + freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));
> freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
> - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);
> + WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
>
> - r = sdma_v5_2_gfx_resume_instance(adev, i, true);
> + r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
>
> -err0:
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> return r;
> }
> --
> 2.25.1
>
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