[PATCH 5/6] drm/radeon: Fix si_upload_smc_data

[Alex Deucher]

On Mon, Aug 4, 2025 at 9:48 AM Timur Kristóf <timur.kristof at gmail.com> wrote:
>
> Backport of the fix to the same amdgpu issue.
>
> The si_upload_smc_data function uses si_write_smc_soft_register
> to set some register values in the SMC, and expects the result
> to be PPSMC_Result_OK which is 1.
>
> The PPSMC_Result_OK / PPSMC_Result_Failed values are used for
> checking the result of a command sent to the SMC.
>
> However, the si_write_smc_soft_register actually doesn't send
> any commands to the SMC and returns zero on success,
> so this check was incorrect.
>
> Fix that by correctly interpreting zero as success.
> This seems to fix an SMC hang that happens in si_set_sw_state.
>
> Fixes: a9e61410921b ("drm/radeon/kms: add dpm support for SI (v7)")
> Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>

Same comment here as the previous patch.

Alex


> ---
>  drivers/gpu/drm/radeon/si_dpm.c | 31 +++++++++++++++++++------------
>  1 file changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
> index 47fba85436a7..8bda1e655468 100644
> --- a/drivers/gpu/drm/radeon/si_dpm.c
> +++ b/drivers/gpu/drm/radeon/si_dpm.c
> @@ -5257,6 +5257,7 @@ static int si_upload_smc_data(struct radeon_device *rdev)
>  {
>         struct radeon_crtc *radeon_crtc = NULL;
>         int i;
> +       int ret;
>
>         if (rdev->pm.dpm.new_active_crtc_count == 0)
>                 return 0;
> @@ -5274,20 +5275,26 @@ static int si_upload_smc_data(struct radeon_device *rdev)
>         if (radeon_crtc->line_time <= 0)
>                 return 0;
>
> -       if (si_write_smc_soft_register(rdev,
> -                                      SI_SMC_SOFT_REGISTER_crtc_index,
> -                                      radeon_crtc->crtc_id) != PPSMC_Result_OK)
> -               return 0;
> +       ret = si_write_smc_soft_register(
> +               rdev,
> +               SI_SMC_SOFT_REGISTER_crtc_index,
> +               radeon_crtc->crtc_id);
> +       if (ret)
> +               return ret;
>
> -       if (si_write_smc_soft_register(rdev,
> -                                      SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
> -                                      radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
> -               return 0;
> +       ret = si_write_smc_soft_register(
> +               rdev,
> +               SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
> +               radeon_crtc->wm_high / radeon_crtc->line_time);
> +       if (ret)
> +               return ret;
>
> -       if (si_write_smc_soft_register(rdev,
> -                                      SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
> -                                      radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
> -               return 0;
> +       ret = si_write_smc_soft_register(
> +               rdev,
> +               SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
> +               radeon_crtc->wm_low / radeon_crtc->line_time);
> +       if (ret)
> +               return ret;
>
>         return 0;
>  }
> --
> 2.50.1
>