[PATCH 1/7] drm/amd/display: Don't overclock DCE 6 by 15%

[Alex Deucher]

On Thu, Jul 31, 2025 at 5:44 AM Timur Kristóf <timur.kristof at gmail.com> wrote:
>
> The extra 15% clock was added as a workaround for a Polaris issue
> which uses DCE 11, and should not have been used on DCE 6 which
> is already hardcoded to the highest possible display clock.
> Unfortunately, the extra 15% was mistakenly copied and kept
> even on code paths which don't affect Polaris.
>
> This commit fixes that and also adds a check to make sure
> not to exceed the maximum DCE 6 display clock.
>
> Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
> Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
> Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)")
> Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index 0267644717b2..cfd7309f2c6a 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -123,11 +123,9 @@ static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
>  {
>         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>         struct dm_pp_power_level_change_request level_change_req;
> -       int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> -       /*TODO: W/A for dal3 linux, investigate why this works */
> -       if (!clk_mgr_dce->dfs_bypass_active)
> -               patched_disp_clk = patched_disp_clk * 115 / 100;
> +       const int max_disp_clk =
> +               clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> +       int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
>
>         level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
>         /* get max clock state from PPLIB */
> --
> 2.50.1
>