[v4 2/3] drm/amd/pm: Add VCN reset support for SMU v13.0.6
Lazar, Lijo
lijo.lazar at amd.com
Wed Aug 13 05:04:47 UTC 2025
On 8/13/2025 9:38 AM, Jesse.Zhang wrote:
> This commit implements VCN reset capability for SMU v13.0.6 with the following changes:
>
> 1. Added new PPSMC message ID (0x5B) for VCN reset in SMU firmware interface
> 2. Extended SMU capabilities to include VCN_RESET support
> 3. Implemented VCN reset support check:
> - Added smu_v13_0_6_reset_vcn_is_supported() function
> 4. Updated SMU v13.0.6 PPT functions to include VCN reset operations
>
> v2: clean up debug info (Alex)
> v3: remove unsupported message and split smu v13.0.6 changes to a separate patch (Lijo)
>
> Suggested-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Ruili Ji <ruiliji2 at amd.com>
> Signed-off-by: Jesse Zhang <Jesse.Zhang at amd.com>
> ---
> .../amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 4 ++--
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 14 ++++++++++++++
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 +
> 3 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
> index 41f268313613..63a088ef7169 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
> @@ -94,9 +94,9 @@
> #define PPSMC_MSG_RmaDueToBadPageThreshold 0x43
> #define PPSMC_MSG_SetThrottlingPolicy 0x44
> #define PPSMC_MSG_ResetSDMA 0x4D
> -#define PPSMC_MSG_ResetVCN 0x4E
> #define PPSMC_MSG_GetStaticMetricsTable 0x59
> -#define PPSMC_Message_Count 0x5A
> +#define PPSMC_MSG_ResetVCN 0x5B
> +#define PPSMC_Message_Count 0x5C
>
> //PPSMC Reset Types for driver msg argument
> #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index 3b4bd7a34d04..db3dd5d5c26f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -436,6 +436,9 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu)
> ((pgm == 0) && (fw_ver >= 0x00557900)) ||
> ((pgm == 4) && (fw_ver >= 0x4557000)))
> smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
> +
> + if ((pgm == 4) && (fw_ver >= 0x04557100))
> + smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
> }
>
> static void smu_v13_0_x_init_caps(struct smu_context *smu)
> @@ -3200,6 +3203,16 @@ static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
> return ret;
> }
>
> +static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu)
> +{
> + bool ret = true;
> +
> + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET)))
This may be simiplified as
return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET));
Thanks,
Lijo
> + ret = false;
> +
> + return ret;
> +}
> +
> static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
> {
> int ret = 0;
> @@ -3888,6 +3901,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
> .reset_sdma = smu_v13_0_6_reset_sdma,
> .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported,
> .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
> + .reset_vcn_is_supported = smu_v13_0_6_reset_vcn_is_supported,
> };
>
> void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> index f39dbfdd7a2f..bcb8246c0804 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> @@ -64,6 +64,7 @@ enum smu_v13_0_6_caps {
> SMU_CAP(RMA_MSG),
> SMU_CAP(ACA_SYND),
> SMU_CAP(SDMA_RESET),
> + SMU_CAP(VCN_RESET),
> SMU_CAP(STATIC_METRICS),
> SMU_CAP(HST_LIMIT_METRICS),
> SMU_CAP(BOARD_VOLTAGE),
More information about the amd-gfx
mailing list