AMDGPU's rings VS Radeon's

[Timur Kristóf]

Hi Alexandre,

On Mon, 2025-08-11 at 18:00 -0400, Alexandre Demers wrote:
> 
> 2- Under AMDGPU, SI's GFX (GFX6) ring size is 2048, while this value
> is 1024 for all the other GFX versions. Under Radeon, the GFX ring
> size values are all the same (1024 * 1024) under Evergreen/SI/CIK/NI
> and others. Is there any reason why SI's GFX6 ring size would be
> twice the size of the other values under AMDGPU?

The ring size determines how many IBs can be submitted by userspace at
once. Originally, RADV developers chose 192 maximum IBs per submission.
As far as I'm aware even today there is no way for userspace to query
the kernel for the number of maximum submitted IBs. (Someone correct me
if I'm wrong about that.)

I think the kernel developers chose to stay compatible with RADV and
the ring sizes are chosen to ensure that there is indeed room for 192
IBs per submission, based on the IB size and the submission frame size.
These are currently not set ideally on GFX6 (and are wrong on GFX7 -
I'll send a patch soon).

That being said, modern versions of RADV will attempt to use "chaining"
to reduce the total number of IBs submitted, when possible. We deem it
possible when the VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT isn't
set on a command buffer. So, practically in a typical Vulkan
application, it would realistically submit just somewhere between 2-5
IBs per submission. However, if an app uses
VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT excessively then RADV will
still submit those IBs individually, up to 192 of them at a time.

In the context of your VCE work, this isn't really relevant as I don't
think RADV can use VCE.

Hope this helps,
Timur