[PATCH 0/7] DC: don't overclock DCE 6-10 and other fixes

[Alex Deucher]

On Sun, Aug 17, 2025 at 11:08 PM Alex Hung <alex.hung at amd.com> wrote:
>
> Reviewed-by: Alex Hung <alex.hung at amd.com>
>
> This patch series was also tested in the promotion test and in CI
> without any regression.

Did you pick these series up or would you like me to?

Alex

>
> On 7/31/25 03:43, Timur Kristóf wrote:
> > This series fixes various issues that I found while trying to
> > get old GPUs with DCE 6 to work well with DC.
> >
> > The most important part of this series is tweaking how
> > the engine clock is set on DCE 6-10.
> >
> > For DCE 6 the maximum according to max_clks_by_state is 600 Mhz,
> > but dce60_validate_bandwidth sets it to 681 MHz, and then
> > dce60_update_clocks further increases it by 15%, resulting in
> > a whopping 783 MHz, which is overall 30% more than what the
> > hardware was supposed to handle. My Tahiti GPU didn't even boot
> > with DC enabled with that clock setting.
> > There is a similar issue with DCE 8-10 too, additionally the
> > dce80_max_clks_by_state data seems to be incorrect, so I changed
> > the maximum to 625 MHz for DCE 8-10, which is what the legacy
> > code uses.
> >
> > I tested these changes and made sure 4K 60Hz (10 bit) output
> > still works with them on the following GPUs:
> >
> > * Tahiti (DCE 6)
> > * Oland (DCE 6.4)
> > * Hawaii (DCE 8)
> > * Tonga, Fiji (DCE 10)
> >
> > I would appreciate if someone from AMD could confirm what the
> > maximum display engine clocks for these parts really are.
> >
> > Other than that, the rest of the series deals with some
> > ligher problems:
> >
> > There are patches to fill the display information on DCE 6-10
> > (previously only filled on DCE 11), such as the first CRTC and
> > its line time, as well as vblank time, display clock etc.
> > These are going to be needed for DPM.
> >
> > It also removes some errors and warnings from the logs which
> > are caused by the VBIOS on old GPUs reporting some information
> > differently, namely some VBIOS seem to lack encoder capability
> > entries for some connectors, as well as the actual amount of
> > connectors on the GPU not matching the number of entries
> > reported by the VBIOS.
> > The DC code base already handles these cases well. They are
> > not actually errors, so we shouldn't spam the logs with them.
> >
> > Finally, there is also a fix for set_pixel_clock_v3 which
> > works slightly differently than the other versions.
> >
> > Timur Kristóf (7):
> >    drm/amd/display: Don't overclock DCE 6 by 15%
> >    drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
> >    drm/amd/display: Find first CRTC and its line time in
> >      dce110_fill_display_configs
> >    drm/amd/display: Fill display clock and vblank time in
> >      dce110_fill_display_configs
> >    drm/amd/display: Don't warn when missing DCE encoder caps
> >    drm/amd/display: Don't print errors for nonexistent connectors
> >    drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3
> >
> >   .../gpu/drm/amd/display/dc/bios/bios_parser.c |  5 +--
> >   .../drm/amd/display/dc/bios/command_table.c   |  2 +-
> >   .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 +++----
> >   .../dc/clk_mgr/dce110/dce110_clk_mgr.c        | 40 +++++++++++--------
> >   .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c  | 10 ++---
> >   drivers/gpu/drm/amd/display/dc/core/dc.c      | 15 ++++++-
> >   .../drm/amd/display/dc/dce/dce_link_encoder.c |  8 ++--
> >   7 files changed, 51 insertions(+), 43 deletions(-)
> >
>