[PATCH 4/8] drm/amd/pm: Fix si_upload_smc_data register programming (v2)

[Timur Kristóf]

Based on some comments in dm_pp_display_configuration
above the crtc_index and line_time fields, these values
are programmed to the SMC to work around an SMC hang
when it switches MCLK.

According to Alex, the Windows driver programs them to:
mclk_change_block_cp_min = 200 / line_time
mclk_change_block_cp_max = 100 / line_time
Let's use the same for the sake of consistency.

Previously we used the watermark values, but it seemed buggy
as the code was mixing up low/high and A/B watermarks, and
was not saving a low watermark value on DCE 6, so
mclk_change_block_cp_max would be always zero previously.

Split this change off from the previous si_upload_smc_data
to make it easier to bisect, in case it causes any issues.

Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
---
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index b16009d342c3..db46fc0817a7 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -5846,11 +5846,11 @@ static int si_upload_smc_data(struct amdgpu_device *adev)
 
 	si_write_smc_soft_register(adev,
 		SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
-		amdgpu_crtc->wm_high / first_crtc_line_time);
+		200 / first_crtc_line_time);
 
 	si_write_smc_soft_register(adev,
 		SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
-		amdgpu_crtc->wm_low / first_crtc_line_time);
+		100 / first_crtc_line_time);
 
 	return 0;
 }
-- 
2.50.1