[PATCH] drm/amd/include : Update MES v12 API header according to new MES features
Shaoyun Liu
shaoyun.liu at amd.com
Sat Feb 1 03:37:43 UTC 2025
1. MES fence_value will be updated in fence_addr if API success, otherwise
upper 32 bit will be used to indicate error code. In any case, MES will
trigger an EOP interrupt with 0xb1 as context id in the interrupt cookie
2. Add RRMT option support which will be used for remote die register access
3. Update set_hw_resource1 for cooperative mode support
4. Add full_sh_mem_config_data for xnack support
Signed-off-by: Shaoyun Liu <shaoyun.liu at amd.com>
---
drivers/gpu/drm/amd/include/mes_v12_api_def.h | 98 ++++++++++++++++++-
1 file changed, 93 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
index c9b2ca5cf75f..05e74f1d7eb1 100644
--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
@@ -105,6 +105,43 @@ struct MES_API_STATUS {
uint64_t api_completion_fence_value;
};
+/*
+ * MES will set api_completion_fence_value in api_completion_fence_addr when
+ * it can successflly process the API. MES will also trigger following interrupt
+ * when it finish process the API no matter success or failed.
+ * Interrupt source id 181 (EOP) with context ID (DW 6 in the int cookie)
+ * set to 0xb1 and context type set to 8. Driver side need to enable
+ * TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to catch this interrupt.
+ * Driver side also need to set enable_mes_fence_int = 1 in set_HW_resource
+ * package to enable this fence interrupt
+ * when the API process failed.
+ * lowre 32 bits set to 0.
+ * higher 32 bits set as follows (bit shift within high 32)
+ * bit 0 - 7 API specific error code.
+ * bit 8 - 15 API OPCODE.
+ * bit 16 - 23 MISC OPCODE if any
+ * bit 24 - 30 ERROR category (API_ERROR_XXX)
+ * bit 31 Set to 1 to indicate error status
+ *
+ */
+enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };
+enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };
+enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };
+enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 };
+
+enum MES_ERROR_CATEGORY_CODE_12
+{
+ MES_ERROR_API = 1,
+ MES_ERROR_SCHEDULING = 2,
+ MES_ERROR_UNKNOWN = 3,
+};
+
+#define MES_ERR_CODE(api_err, opcode, misc_op, category) \
+ ((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \
+ misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \
+ category << MES_ERROR_CATEGORY_SHIFT_12 | \
+ 1 << MES_API_STATUS_ERROR_SHIFT_12) << 32);
+
enum { MAX_COMPUTE_PIPES = 8 };
enum { MAX_GFX_PIPES = 2 };
@@ -248,7 +285,8 @@ union MESAPI_SET_HW_RESOURCES {
uint32_t enable_mes_sch_stb_log : 1;
uint32_t limit_single_process : 1;
uint32_t unmapped_doorbell_handling: 2;
- uint32_t reserved : 11;
+ uint32_t enable_mes_fence_int: 1;
+ uint32_t reserved : 10;
};
uint32_t uint32_all;
};
@@ -270,7 +308,8 @@ union MESAPI_SET_HW_RESOURCES_1 {
union {
struct {
uint32_t enable_mes_debug_ctx : 1;
- uint32_t reserved : 31;
+ uint32_t mes_coop_mode : 1; /* 0: non-coop; 1: coop */
+ uint32_t reserved : 30
};
uint32_t uint32_all;
};
@@ -278,6 +317,8 @@ union MESAPI_SET_HW_RESOURCES_1 {
uint32_t mes_debug_ctx_size;
/* unit is 100ms */
uint32_t mes_kiq_unmap_timeout;
+ /* shared buffer of master/slaves, valid if mes_coop_mode=1 */
+ uint64_t coop_sch_shared_mc_addr;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
@@ -341,6 +382,7 @@ union MESAPI__ADD_QUEUE {
uint32_t pipe_id; //used for mapping legacy kernel queue
uint32_t queue_id;
uint32_t alignment_mode_setting;
+ uint32_t full_sh_mem_config_data;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
@@ -629,6 +671,7 @@ union MESAPI__SET_DEBUG_VMID {
uint32_t process_context_array_index;
uint32_t alignment_mode_setting;
+ uint32_t full_sh_mem_config_data;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
@@ -653,9 +696,51 @@ enum MESAPI_MISC_OPCODE {
enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20};
-struct WRITE_REG {
- uint32_t reg_offset;
- uint32_t reg_value;
+/*
+ * RRMT(Register Remapping Table), allow the firmware to modify the upper address
+ * to correctly steer the register transaction to either the local AID/XCD or
+ * remote MID on SMN.
+ * mode : Mode of operation for RRMT
+ * 0=Local XCD
+ * 1=Remote/Local AID
+ * 2=Remote XCD
+ * 3=Remote MID
+ * mid_die_id : Physical ID number of the Multimedia IO Die (MID) to be accessed for RRMT.
+ * 0=MID0.
+ * 1=MID1
+ * xcd_die_id : Virtual ID number of the Accelerated Compute Die (XCD)
+ * to be accessed for RRMT. For MI400, there are 2 Active
+ * Interposer Die (AID) each with 4 XCDs. The number of
+ * available XCDs depends on the Partition Mode programmed
+ * by the Secure Processor
+ * 0=XCD0.
+ * 1=XCD1.
+ * 2=XCD2.
+ * 3=XCD3.
+ * 4=XCD4.
+ * 5=XCD5.
+ * 6=XCD6.
+ * 7=XCD7.
+ *
+ */
+struct RRMT_OPTION
+{
+ union {
+ struct {
+ uint32_t mode : 4;
+ uint32_t mid_die_id : 4;
+ uint32_t xcd_die_id : 4;
+ };
+ uint32_t all;
+ };
+};
+
+
+struct WRITE_REG
+{
+ uint32_t reg_offset;
+ uint32_t reg_value;
+ struct RRMT_OPTION rrmt_opt;
};
struct READ_REG {
@@ -668,6 +753,7 @@ struct READ_REG {
} bits;
uint32_t all;
} option;
+ struct RRMT_OPTION rrmt_opt;
};
struct INV_GART {
@@ -693,6 +779,8 @@ struct WAIT_REG_MEM {
uint32_t mask;
uint32_t reg_offset1;
uint32_t reg_offset2;
+ struct RRMT_OPTION rrmt_opt1; /* for reg1 */
+ struct RRMT_OPTION rrmt_opt2; /* for reg2 */
};
struct SET_SHADER_DEBUGGER {
--
2.34.1
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