[PATCH 18/44] drm/amdgpu/vcn4.0.5: convert internal functions to use vcn_inst
Boyuan Zhang
Boyuan.Zhang at amd.com
Wed Feb 5 15:04:10 UTC 2025
On 2025-01-31 11:57, Alex Deucher wrote:
> Pass the vcn instance structure to these functions rather
> than adev and the instance number.
>
> TODO: clean up the function internals to use the vinst state
> directly rather than accessing it indirectly via adev->vcn.inst[].
>
> Signed-off-by: Alex Deucher<alexander.deucher at amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang at amd.com>
<mailto:Boyuan.Zhang at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 111 ++++++++++++++----------
> 1 file changed, 64 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index c3a2826a59631..295f39b2222d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -385,13 +385,14 @@ static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block)
> /**
> * vcn_v4_0_5_mc_resume - memory controller programming
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Let the VCN memory controller know it's offsets
> */
> -static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> @@ -445,14 +446,16 @@ static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)
> /**
> * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode
> *
> - * @adev: amdgpu_device pointer
> - * @inst_idx: instance number index
> + * @vinst: VCN instance
> * @indirect: indirectly write sram
> *
> * Let the VCN memory controller know it's offsets with dpg mode
> */
> -static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
> +static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
> + bool indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> @@ -559,13 +562,14 @@ static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
> /**
> * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Disable static power gating for VCN block
> */
> -static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data = 0;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> @@ -618,13 +622,14 @@ static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, i
> /**
> * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Enable static power gating for VCN block
> */
> -static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> @@ -660,13 +665,14 @@ static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, in
> /**
> * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Disable clock gating for VCN block
> */
> -static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data;
>
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -771,16 +777,18 @@ static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst
> /**
> * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
> *
> - * @adev: amdgpu_device pointer
> + * @vinst: VCN instance
> * @sram_sel: sram select
> - * @inst_idx: instance number index
> * @indirect: indirectly write sram
> *
> * Disable clock gating for VCN block with dpg mode
> */
> -static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
> - int inst_idx, uint8_t indirect)
> +static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
> + uint8_t sram_sel,
> + uint8_t indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> uint32_t reg_data = 0;
>
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -828,13 +836,14 @@ static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev,
> /**
> * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Enable clock gating for VCN block
> */
> -static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data;
>
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -887,14 +896,16 @@ static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
> /**
> * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode
> *
> - * @adev: amdgpu_device pointer
> - * @inst_idx: instance number index
> + * @vinst: VCN instance
> * @indirect: indirectly write sram
> *
> * Start VCN block with dpg mode
> */
> -static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
> +static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
> + bool indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> @@ -913,7 +924,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
> (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
>
> /* enable clock gating */
> - vcn_v4_0_5_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
> + vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect);
>
> /* enable VCPU clock */
> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> @@ -961,7 +972,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>
> - vcn_v4_0_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
> + vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect);
>
> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> @@ -1014,13 +1025,14 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
> /**
> * vcn_v4_0_5_start - VCN start
> *
> - * @adev: amdgpu_device pointer
> - * @i: instance to start
> + * @vinst: VCN instance
> *
> * Start VCN block
> */
> -static int vcn_v4_0_5_start(struct amdgpu_device *adev, int i)
> +static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int i = vinst->inst;
> volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> @@ -1035,17 +1047,17 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev, int i)
> fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> - return vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.inst[i].indirect_sram);
> + return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
>
> /* disable VCN power gating */
> - vcn_v4_0_5_disable_static_power_gating(adev, i);
> + vcn_v4_0_5_disable_static_power_gating(vinst);
>
> /* set VCN status busy */
> tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
> WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
>
> /* SW clock gating */
> - vcn_v4_0_5_disable_clock_gating(adev, i);
> + vcn_v4_0_5_disable_clock_gating(vinst);
>
> /* enable VCPU clock */
> WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
> @@ -1098,7 +1110,7 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev, int i)
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
>
> - vcn_v4_0_5_mc_resume(adev, i);
> + vcn_v4_0_5_mc_resume(vinst);
>
> /* VCN global tiling registers */
> WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
> @@ -1194,13 +1206,14 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev, int i)
> /**
> * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode
> *
> - * @adev: amdgpu_device pointer
> - * @inst_idx: instance number index
> + * @vinst: VCN instance
> *
> * Stop VCN block with dpg mode
> */
> -static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
> +static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> uint32_t tmp;
>
> /* Wait for power status to be 1 */
> @@ -1222,13 +1235,14 @@ static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
> /**
> * vcn_v4_0_5_stop - VCN stop
> *
> - * @adev: amdgpu_device pointer
> - * @i: instance to stop
> + * @vinst: VCN instance
> *
> * Stop VCN block
> */
> -static int vcn_v4_0_5_stop(struct amdgpu_device *adev, int i)
> +static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int i = vinst->inst;
> volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> uint32_t tmp;
> int r = 0;
> @@ -1240,7 +1254,7 @@ static int vcn_v4_0_5_stop(struct amdgpu_device *adev, int i)
> fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> - vcn_v4_0_5_stop_dpg_mode(adev, i);
> + vcn_v4_0_5_stop_dpg_mode(vinst);
> return 0;
> }
>
> @@ -1293,10 +1307,10 @@ static int vcn_v4_0_5_stop(struct amdgpu_device *adev, int i)
> WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
>
> /* apply HW clock gating */
> - vcn_v4_0_5_enable_clock_gating(adev, i);
> + vcn_v4_0_5_enable_clock_gating(vinst);
>
> /* enable VCN power gating */
> - vcn_v4_0_5_enable_static_power_gating(adev, i);
> + vcn_v4_0_5_enable_static_power_gating(vinst);
>
> if (adev->pm.dpm_enabled)
> amdgpu_dpm_enable_vcn(adev, false, i);
> @@ -1526,15 +1540,17 @@ static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> int i;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
> +
> if (adev->vcn.harvest_config & (1 << i))
> continue;
>
> if (enable) {
> if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
> return -EBUSY;
> - vcn_v4_0_5_enable_clock_gating(adev, i);
> + vcn_v4_0_5_enable_clock_gating(vinst);
> } else {
> - vcn_v4_0_5_disable_clock_gating(adev, i);
> + vcn_v4_0_5_disable_clock_gating(vinst);
> }
> }
>
> @@ -1546,15 +1562,16 @@ static int vcn_v4_0_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_bloc
> int i)
> {
> struct amdgpu_device *adev = ip_block->adev;
> + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
> int ret = 0;
>
> if (state == adev->vcn.inst[i].cur_state)
> return 0;
>
> if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v4_0_5_stop(adev, i);
> + ret = vcn_v4_0_5_stop(vinst);
> else
> - ret = vcn_v4_0_5_start(adev, i);
> + ret = vcn_v4_0_5_start(vinst);
>
> if (!ret)
> adev->vcn.inst[i].cur_state = state;
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