[PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once

[Alex Deucher]

Allocate the buffer at sw init time so we don't alloc
and free it for every suspend/resume or reset cycle.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 39 +++++++++++++-------------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 8dbab3834d82d..6db88584dd529 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -678,9 +678,6 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
 
 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
 {
-	unsigned int alloc_size = AMDGPU_GPU_PAGE_SIZE;
-	int ret = 0;
-	struct amdgpu_device *adev = mes->adev;
 	union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
 
 	memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
@@ -689,17 +686,6 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
 	mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
 	mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
-
-	ret = amdgpu_bo_create_kernel(adev, alloc_size, PAGE_SIZE,
-				AMDGPU_GEM_DOMAIN_VRAM,
-				&mes->resource_1,
-				&mes->resource_1_gpu_addr,
-				&mes->resource_1_addr);
-	if (ret) {
-		dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
-		return ret;
-	}
-
 	mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr =
 		mes->resource_1_gpu_addr;
 
@@ -1550,6 +1536,20 @@ static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
 			return r;
 	}
 
+	if (adev->enable_uni_mes) {
+		int ret;
+
+		ret = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
+					      AMDGPU_GEM_DOMAIN_VRAM,
+					      &adev->mes.resource_1,
+					      &adev->mes.resource_1_gpu_addr,
+					      &adev->mes.resource_1_addr);
+		if (ret) {
+			dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
@@ -1558,6 +1558,11 @@ static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
 	struct amdgpu_device *adev = ip_block->adev;
 	int pipe;
 
+	if (adev->enable_uni_mes)
+		amdgpu_bo_free_kernel(&adev->mes.resource_1,
+				      &adev->mes.resource_1_gpu_addr,
+				      &adev->mes.resource_1_addr);
+
 	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 		kfree(adev->mes.mqd_backup[pipe]);
 
@@ -1786,12 +1791,6 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
 
 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
 {
-	struct amdgpu_device *adev = ip_block->adev;
-
-	if (adev->enable_uni_mes)
-		amdgpu_bo_free_kernel(&adev->mes.resource_1,
-				      &adev->mes.resource_1_gpu_addr,
-				      &adev->mes.resource_1_addr);
 	return 0;
 }
 
-- 
2.48.1