[PATCH 1/2] drm/amdgpu/mes11: allocate hw_resource_1 buffer once

[Liu, Shaoyun]

[AMD Official Use Only - AMD Internal Distribution Only]

Looks good to me .
Reviewed-by: Shaoyun.liu < shaouyun.liu at amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Friday, February 14, 2025 10:19 AM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: [PATCH 1/2] drm/amdgpu/mes11: allocate hw_resource_1 buffer once

Allocate the buffer at sw init time so we don't alloc and free it for every suspend/resume or reset cycle.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 52 +++++++++++++-------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 26af0af718b5e..530371e6a7aee 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -64,6 +64,7 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);

 #define MES_EOP_SIZE   2048
 #define GFX_MES_DRAM_SIZE      0x80000
+#define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE)

 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)  { @@ -743,11 +744,6 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)

 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)  {
-       unsigned int hw_rsrc_size = 128 * AMDGPU_GPU_PAGE_SIZE;
-       /* add a page for the cleaner shader fence */
-       unsigned int alloc_size = hw_rsrc_size + AMDGPU_GPU_PAGE_SIZE;
-       int ret = 0;
-       struct amdgpu_device *adev = mes->adev;
        union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
        memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));

@@ -755,21 +751,10 @@ static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
        mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
        mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
        mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
-
-       ret = amdgpu_bo_create_kernel(adev, alloc_size, PAGE_SIZE,
-                               AMDGPU_GEM_DOMAIN_VRAM,
-                               &mes->resource_1,
-                               &mes->resource_1_gpu_addr,
-                               &mes->resource_1_addr);
-       if (ret) {
-               dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
-               return ret;
-       }
-
        mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
-       mes_set_hw_res_pkt.mes_info_ctx_size = hw_rsrc_size;
+       mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;
        mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr =
-               mes->resource_1_gpu_addr + hw_rsrc_size;
+               mes->resource_1_gpu_addr + MES11_HW_RESOURCE_1_SIZE;

        return mes_v11_0_submit_pkt_and_poll_completion(mes,
                        &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), @@ -1442,6 +1427,23 @@ static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        if (r)
                return r;

+       if (amdgpu_sriov_is_mes_info_enable(adev) ||
+           adev->gfx.enable_cleaner_shader) {
+               int ret;
+
+               ret = amdgpu_bo_create_kernel(adev,
+                                             MES11_HW_RESOURCE_1_SIZE + AMDGPU_GPU_PAGE_SIZE,
+                                             PAGE_SIZE,
+                                             AMDGPU_GEM_DOMAIN_VRAM,
+                                             &adev->mes.resource_1,
+                                             &adev->mes.resource_1_gpu_addr,
+                                             &adev->mes.resource_1_addr);
+               if (ret) {
+                       dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
+                       return ret;
+               }
+       }
+
        return 0;
 }

@@ -1450,6 +1452,12 @@ static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
        struct amdgpu_device *adev = ip_block->adev;
        int pipe;

+       if (amdgpu_sriov_is_mes_info_enable(adev) ||
+           adev->gfx.enable_cleaner_shader) {
+               amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
+                                     &adev->mes.resource_1_addr);
+       }
+
        for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
                kfree(adev->mes.mqd_backup[pipe]);

@@ -1670,14 +1678,6 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)

 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)  {
-       struct amdgpu_device *adev = ip_block->adev;
-
-       if (amdgpu_sriov_is_mes_info_enable(adev) ||
-           adev->gfx.enable_cleaner_shader) {
-               amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
-                                     &adev->mes.resource_1_addr);
-       }
-
        return 0;
 }

--
2.48.1