[PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once
Liu, Shaoyun
Shaoyun.Liu at amd.com
Fri Feb 14 17:46:27 UTC 2025
[AMD Official Use Only - AMD Internal Distribution Only]
Oh, you right. It's only for unified MES , for none-unified , it will still use the kiq from CP directly on pipe1 . So there is no MES API for it at all . It's my fault . please ignore my previous comments . Your current change for this serials is good enough.
Regards
Shaoyun.liu
From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Friday, February 14, 2025 12:42 PM
To: Liu, Shaoyun <Shaoyun.Liu at amd.com>; amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once
[AMD Official Use Only - AMD Internal Distribution Only]
Does it matter which pipe we use for these packets?
Alex
________________________________
From: Liu, Shaoyun <Shaoyun.Liu at amd.com<mailto:Shaoyun.Liu at amd.com>>
Sent: Friday, February 14, 2025 12:36 PM
To: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>; amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>
Subject: RE: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once
[AMD Official Use Only - AMD Internal Distribution Only]
Ok . From MES point of view , we expecting both set_hw_resource and set_hw_resource_1 been called all the time.
Reviewed-by: Shaoyun.liu <Shaoyun.liu at amd.com<mailto:Shaoyun.liu at amd.com>>
From: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>
Sent: Friday, February 14, 2025 11:53 AM
To: Liu, Shaoyun <Shaoyun.Liu at amd.com<mailto:Shaoyun.Liu at amd.com>>; amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>
Subject: Re: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once
[AMD Official Use Only - AMD Internal Distribution Only]
I can add that as a follow up patch as I don't want to change the current behavior to avoid a potential regression. Should we submit both the resource and resource_1 packets all the time?
Thanks,
Alex
________________________________
From: Liu, Shaoyun <Shaoyun.Liu at amd.com<mailto:Shaoyun.Liu at amd.com>>
Sent: Friday, February 14, 2025 11:45 AM
To: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>; amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>
Subject: RE: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once
[AMD Official Use Only - AMD Internal Distribution Only]
I'd suggest remove the enable_uni_mes check, set_hw_resource_1 is always required for gfx12 and up. Especially after add the cleaner_shader_fence_addr there.
Regards
Shaoyun.liu
-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org<mailto:amd-gfx-bounces at lists.freedesktop.org>> On Behalf Of Alex Deucher
Sent: Friday, February 14, 2025 10:19 AM
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>
Subject: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once
Allocate the buffer at sw init time so we don't alloc and free it for every suspend/resume or reset cycle.
Signed-off-by: Alex Deucher <alexander.deucher at amd.com<mailto:alexander.deucher at amd.com>>
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 39 +++++++++++++-------------
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 8dbab3834d82d..6db88584dd529 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -678,9 +678,6 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) {
- unsigned int alloc_size = AMDGPU_GPU_PAGE_SIZE;
- int ret = 0;
- struct amdgpu_device *adev = mes->adev;
union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); @@ -689,17 +686,6 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
-
- ret = amdgpu_bo_create_kernel(adev, alloc_size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &mes->resource_1,
- &mes->resource_1_gpu_addr,
- &mes->resource_1_addr);
- if (ret) {
- dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
- return ret;
- }
-
mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr =
mes->resource_1_gpu_addr;
@@ -1550,6 +1536,20 @@ static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
return r;
}
+ if (adev->enable_uni_mes) {
+ int ret;
+
+ ret = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &adev->mes.resource_1,
+ &adev->mes.resource_1_gpu_addr,
+ &adev->mes.resource_1_addr);
+ if (ret) {
+ dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
+ return ret;
+ }
+ }
+
return 0;
}
@@ -1558,6 +1558,11 @@ static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int pipe;
+ if (adev->enable_uni_mes)
+ amdgpu_bo_free_kernel(&adev->mes.resource_1,
+ &adev->mes.resource_1_gpu_addr,
+ &adev->mes.resource_1_addr);
+
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
kfree(adev->mes.mqd_backup[pipe]);
@@ -1786,12 +1791,6 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) {
- struct amdgpu_device *adev = ip_block->adev;
-
- if (adev->enable_uni_mes)
- amdgpu_bo_free_kernel(&adev->mes.resource_1,
- &adev->mes.resource_1_gpu_addr,
- &adev->mes.resource_1_addr);
return 0;
}
--
2.48.1
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20250214/28fbf195/attachment-0001.htm>
More information about the amd-gfx
mailing list