[PATCH 00/16] DC Patches February 14, 2025

Wheeler, Daniel Daniel.Wheeler at amd.com
Tue Feb 18 16:10:32 UTC 2025 

[Public]

Hi all,

This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.

APU
        * Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
        * Single Display DP (SST DSC) -> 4k144hz, 4k240hz
        * Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
        * Thunderbolt -> LG Ultrafine 5k
        * MST DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 2x 4k60hz displays
        * USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
        * SST PCON -> Club3D CAC-1085 + 1x 4k 144hz, FRL3, at a max resolution supported by the dongle of 4k 120hz YUV420 12bpc.
        * MST PCON -> 1x 4k 144hz, FRL3, at a max resolution supported by the adapter of 4k 120hz RGB 8bpc.

DGPU
        * Single Display DP (SST DSC) -> 4k144hz, 4k240hz
        * Multiple Display DP -> 4k240hz + 4k144hz
        * MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
        * MST DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)

The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
        * Changing display configurations and settings
        * Video/Audio playback
        * Benchmark testing
        * Suspend/Resume testing
        * Feature testing (Freesync, HDCP, etc.)

Automated testing includes (but is not limited to)
        * Script testing (scripts to automate some of the manual checks)
        * IGT testing

The testing is mainly tested on the following displays, but occasionally there are tests with other displays
        * Samsung G8 Neo 4k240hz
        * Samsung QN55QN95B 4k 120hz
        * Acer XV322QKKV 4k144hz
        * HP U27 4k Wireless 4k60hz
        * LG 27UD58B 4k60hz
        * LG 32UN650WA 4k60hz
        * LG Ultrafine 5k 5k60hz
        * AU Optronics B140HAN01.1 1080p 60hz eDP
        * AU Optronics B160UAN01.J 1920x1200 165hz eDP
        * AU Optronics B160QAN02.L 2560x1600 120hz eDP

The patchset consists of the amd-staging-drm-next branch (Head commit - 6621ee40ced88ecf6b9901e26a11ed1b56e9e9f5 -> drm/amd/display: 3.2.320) with new patches added on top of it.

Tested on Ubuntu 24.04.1, on Wayland and X11, using KDE Plasma and Gnome.

Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>



Thank you,

Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com

-----Original Message-----
From: Roman.Li at amd.com <Roman.Li at amd.com>
Sent: Friday, February 14, 2025 10:00 AM
To: amd-gfx at lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland at amd.com>; Li, Sun peng (Leo) <Sunpeng.Li at amd.com>; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Li, Roman <Roman.Li at amd.com>; Lin, Wayne <Wayne.Lin at amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung at amd.com>; Zuo, Jerry <Jerry.Zuo at amd.com>; Mohamed, Zaeem <Zaeem.Mohamed at amd.com>; Chiu, Solomon <Solomon.Chiu at amd.com>; Wheeler, Daniel <Daniel.Wheeler at amd.com>; Li, Roman <Roman.Li at amd.com>
Subject: [PATCH 00/16] DC Patches February 14, 2025

From: Roman Li <Roman.Li at amd.com>

Summary:

* Add support for disconnected eDP streams
* Add log for MALL entry on DCN32x
* Add DCC/Tiling reset helper for DCN and DCE
* Guard against setting dispclk low when active
* Other minor fixes

Cc: Daniel Wheeler <daniel.wheeler at amd.com>

Alex Hung (1):
  drm/amd/display: Print seamless boot message in
    mark_seamless_boot_stream

Aurabindo Pillai (1):
  drm/amd/display: Add log for MALL entry on DCN32x

George Shen (1):
  drm/amd/display: Read LTTPR ALPM caps during link cap retrieval

Harry VanZyllDeJong (1):
  drm/amd/display: Add support for disconnected eDP streams

Harry Wentland (1):
  drm/amd/display: Don't treat wb connector as physical in
    create_validate_stream_for_sink

Ilya Bakoulin (1):
  drm/amd/display: Support BT2020 YCbCr fullrange

Leo Zeng (1):
  Revert "drm/amd/display: Request HW cursor on DCN3.2 with SubVP"

Nicholas Kazlauskas (1):
  drm/amd/display: Guard against setting dispclk low when active

Oleh Kuzhylnyi (1):
  drm/amd/display: Add total_num_dpps_required field to informative
    structure

Ovidiu Bunea (1):
  drm/amd/display: Exit idle optimizations before accessing PHY

Peichen Huang (1):
  drm/amd/display: dpia should avoid encoder used by dp2

Rodrigo Siqueira (4):
  drm/amd/display: Add DCC/Tiling reset helper for DCN and DCE
  drm/amd/display: Rename panic function
  drm/amd/display: Add clear DCC and Tiling callback for DCN
  drm/amd/display: Add clear DCC and Tiling callback for DCE

Taimur Hassan (1):
  drm/amd/display: 3.2.321

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++++++++++++-------  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  2 +-  .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  2 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  6 ++--
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  2 +-
 .../gpu/drm/amd/display/dc/basics/dc_common.c |  3 +-  .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  | 13 +++++---  .../drm/amd/display/dc/core/dc_hw_sequencer.c |  5 +--  .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 16 ++--------  .../gpu/drm/amd/display/dc/core/dc_resource.c |  8 +++--  .../gpu/drm/amd/display/dc/core/dc_surface.c  | 31 +++---------------
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  | 12 +++++++  drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |  4 ++-
 drivers/gpu/drm/amd/display/dc/dc_plane.h     |  4 +--
 .../amd/display/dc/dce/dce_stream_encoder.c   |  3 +-
 .../amd/display/dc/dce60/dce60_hw_sequencer.c |  1 +
 .../dc/dio/dcn10/dcn10_stream_encoder.c       |  3 +-
 .../dc/dio/dcn401/dcn401_dio_stream_encoder.c |  3 +-  .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  |  1 -  .../display/dc/dml2/dml21/inc/dml_top_types.h |  4 +++
 .../src/dml2_core/dml2_core_dcn4_calcs.c      |  5 ++-
 .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c   |  3 +-
 .../amd/display/dc/hwss/dce100/dce100_hwseq.c | 30 +++++++++++++++++  .../amd/display/dc/hwss/dce100/dce100_hwseq.h |  4 +++  .../amd/display/dc/hwss/dce110/dce110_hwseq.c |  7 ++++  .../amd/display/dc/hwss/dce120/dce120_hwseq.c |  2 ++
 .../amd/display/dc/hwss/dce80/dce80_hwseq.c   |  1 +
 .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c   | 29 +++++++++++++++++
 .../amd/display/dc/hwss/dcn10/dcn10_hwseq.h   |  4 +++
 .../amd/display/dc/hwss/dcn10/dcn10_init.c    |  1 +
 .../amd/display/dc/hwss/dcn20/dcn20_init.c    |  1 +
 .../amd/display/dc/hwss/dcn201/dcn201_init.c  |  1 +
 .../amd/display/dc/hwss/dcn21/dcn21_init.c    |  1 +
 .../amd/display/dc/hwss/dcn30/dcn30_init.c    |  1 +
 .../amd/display/dc/hwss/dcn301/dcn301_init.c  |  1 +
 .../amd/display/dc/hwss/dcn31/dcn31_init.c    |  1 +
 .../amd/display/dc/hwss/dcn314/dcn314_init.c  |  1 +
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c   |  2 ++
 .../amd/display/dc/hwss/dcn32/dcn32_init.c    |  1 +
 .../amd/display/dc/hwss/dcn35/dcn35_init.c    |  1 +
 .../amd/display/dc/hwss/dcn351/dcn351_init.c  |  1 +  .../amd/display/dc/hwss/dcn401/dcn401_init.c  |  1 +
 .../drm/amd/display/dc/hwss/hw_sequencer.h    |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |  6 +++-
 .../dc/link/protocols/link_dp_capability.c    | 12 ++++---
 .../display/modules/info_packet/info_packet.c |  4 +--
 47 files changed, 192 insertions(+), 87 deletions(-)

--
2.34.1

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