[PATCH 3/6] drm/amdgpu: complete dce_v6_0_set_crtc_vline_interrupt_state() in DCE6

[Alex Deucher]

On Thu, Feb 27, 2025 at 12:23 AM Alexandre Demers
<alexandre.f.demers at gmail.com> wrote:
>
> dce_v6_0_set_crtc_vline_interrupt_state() was empty without any info to
> inform the user.

Doesn't hurt to fill it in, but nothing uses the vline interrupt at
the moment.  Might be better to just remove it from all of the non-DC
display code.

Alex


>
> Based on DCE8 and DCE10 code.
>
> Signed-off-by: Alexandre Demers <alexandre.f.demers at gmail.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 44 +++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 254cb73324c6..e805c4f9222c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2957,7 +2957,51 @@ static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
>                                                     int crtc,
>                                                     enum amdgpu_interrupt_state state)
>  {
> +       u32 reg_block, lb_interrupt_mask;
>
> +       if (crtc >= adev->mode_info.num_crtc) {
> +               DRM_DEBUG("invalid crtc %d\n", crtc);
> +               return;
> +       }
> +
> +       switch (crtc) {
> +       case 0:
> +               reg_block = CRTC0_REGISTER_OFFSET;
> +               break;
> +       case 1:
> +               reg_block = CRTC1_REGISTER_OFFSET;
> +               break;
> +       case 2:
> +               reg_block = CRTC2_REGISTER_OFFSET;
> +               break;
> +       case 3:
> +               reg_block = CRTC3_REGISTER_OFFSET;
> +               break;
> +       case 4:
> +               reg_block = CRTC4_REGISTER_OFFSET;
> +               break;
> +       case 5:
> +               reg_block = CRTC5_REGISTER_OFFSET;
> +               break;
> +       default:
> +               DRM_DEBUG("invalid crtc %d\n", crtc);
> +               return;
> +       }
> +
> +       switch (state) {
> +       case AMDGPU_IRQ_STATE_DISABLE:
> +               lb_interrupt_mask = RREG32(mmINT_MASK + reg_block);
> +               lb_interrupt_mask &= ~VLINE_INT_MASK;
> +               WREG32(mmINT_MASK + reg_block, lb_interrupt_mask);
> +               break;
> +       case AMDGPU_IRQ_STATE_ENABLE:
> +               lb_interrupt_mask = RREG32(mmINT_MASK + reg_block);
> +               lb_interrupt_mask |= VLINE_INT_MASK;
> +               WREG32(mmINT_MASK + reg_block, lb_interrupt_mask);
> +               break;
> +       default:
> +               break;
> +       }
>  }
>
>  static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
> --
> 2.48.1
>