[PATCH 1/2 V2] drm/amdgpu/gfx10: implement iqueue reset via MMIO

[Zhang, Jesse(Jie)]

[AMD Official Use Only - AMD Internal Distribution Only]

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-----Original Message-----
From: Jesse.zhang at amd.com <jesse.zhang at amd.com>
Sent: Friday, January 10, 2025 1:22 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Huang, Tim <Tim.Huang at amd.com>; Zhu, Jiadong <Jiadong.Zhu at amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang at amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang at amd.com>
Subject: [PATCH 1/2 V2] drm/amdgpu/gfx10: implement iqueue reset via MMIO

From: "Jesse.zhang at amd.com" <Jesse.zhang at amd.com>

Using mmio to do queue reset.

v2: Alignment this function with gfx9/gfx9.4.3.

Signed-off-by: Jesse Zhang <jesse.zhang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 34 ++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5ba263fe5512..6157e1126030 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3790,12 +3790,46 @@ static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
        gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);  }

+static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,
+                                       uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
+                                       uint32_t xcc_id, uint32_t vmid)
+{
+       struct amdgpu_device *adev = kiq_ring->adev;
+       unsigned i;
+
+       /* enter save mode */
+       amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
+       mutex_lock(&adev->srbm_mutex);
+       nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);
+
+       if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
+               WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);
+               WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);
+               /* wait till dequeue take effects */
+               for (i = 0; i < adev->usec_timeout; i++) {
+                       if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
+                               break;
+                       udelay(1);
+               }
+               if (i >= adev->usec_timeout)
+                       dev_err(adev->dev, "fail to wait on hqd deactive\n");
+       } else {
+               dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);
+       }
+
+       nv_grbm_select(adev, 0, 0, 0, 0);
+       mutex_unlock(&adev->srbm_mutex);
+       /* exit safe mode */
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0); }
+
 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
        .kiq_set_resources = gfx10_kiq_set_resources,
        .kiq_map_queues = gfx10_kiq_map_queues,
        .kiq_unmap_queues = gfx10_kiq_unmap_queues,
        .kiq_query_status = gfx10_kiq_query_status,
        .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
+       .kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,
        .set_resources_size = 8,
        .map_queues_size = 7,
        .unmap_queues_size = 6,
--
2.25.1