[PATCH] drm/amd/amdgpu: Enable scratch data dump for mes 12

[Alex Deucher]

On Tue, Jan 14, 2025 at 11:02 PM Shaoyun Liu <shaoyun.liu at amd.com> wrote:
>
> MES internal will check CP_MES_MSCRATCH_LO/HI register to set scratch data location
> during ucode start, driver side need to start the MES one by one with different
> setting for each pipe
>
> Signed-off-by: Shaoyun Liu <shaoyun.liu at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 43 +++++++++++++++++++-------
>  1 file changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> index d24a0e7fff15..f79edff19333 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> @@ -992,29 +992,47 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
>         uint32_t pipe, data = 0;
>
>         if (enable) {
> -               data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
> -               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
> -               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
> -               WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
> -
>                 mutex_lock(&adev->srbm_mutex);
>                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
>                         soc21_grbm_select(adev, 3, pipe, 0, 0);
> +                       if (amdgpu_mes_log_enable) {
> +                               uint32_t log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
> +                               /* In case uni mes is not enabled, only program for pipe 0 */
> +                               if (adev->mes.event_log_size >= (pipe + 1) * log_size) {
> +                                       WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
> +                                               lower_32_bits(adev->mes.event_log_gpu_addr + pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));
> +                                       WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
> +                                               upper_32_bits(adev->mes.event_log_gpu_addr + pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));
> +                                       dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
> +                                               RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
> +                                               RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
> +                               }
> +                       }
> +
> +                       data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
> +                       if (pipe == 0)
> +                               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
> +                       else
> +                               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
> +                       WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
>
>                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
>                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
>                                      lower_32_bits(ucode_addr));
>                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
>                                      upper_32_bits(ucode_addr));
> +
> +                       /* unhalt MES and activate one pipe each loop */
> +                       if (pipe == 0)
> +                               data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
> +                       else
> +                               data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
> +                       WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
> +
>                 }
>                 soc21_grbm_select(adev, 0, 0, 0, 0);
>                 mutex_unlock(&adev->srbm_mutex);
>
> -               /* unhalt MES and activate pipe0 */
> -               data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
> -               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
> -               WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
> -
>                 if (amdgpu_emu_mode)
>                         msleep(100);
>                 else if (adev->enable_uni_mes)
> @@ -1488,8 +1506,9 @@ static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
>         adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
>         adev->mes.enable_legacy_queue_map = true;
>
> -       adev->mes.event_log_size = adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE) : AMDGPU_MES_LOG_BUFFER_SIZE;
> -
> +       adev->mes.event_log_size = adev->enable_uni_mes ?
> +               (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) :
> +               (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);
>         r = amdgpu_mes_init(adev);
>         if (r)
>                 return r;
> --
> 2.34.1
>