[PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0

[Zhang, Hawking]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: Kamal, Asad <Asad.Kamal at amd.com>
Sent: Wednesday, January 22, 2025 17:56
To: amd-gfx at lists.freedesktop.org; Lazar, Lijo <Lijo.Lazar at amd.com>
Cc: Ma, Le <Le.Ma at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; Zhang, Morris <Shiwu.Zhang at amd.com>; Kamal, Asad <Asad.Kamal at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0

Update power management & clk attributes for gc_v_9_5_0

Signed-off-by: Asad Kamal <asad.kamal at amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e8ae7681bf0a..0aca0803514e 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2006,9 +2006,10 @@ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdg
                return 0;
        }

-       /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */
+       /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0 SRIOV/BM
+support */
        if (gc_ver == IP_VERSION(9, 4, 3) ||
-           gc_ver == IP_VERSION(9, 4, 4)) {
+           gc_ver == IP_VERSION(9, 4, 4) ||
+           gc_ver == IP_VERSION(9, 5, 0)) {
                if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
                        *states = ATTR_STATE_UNSUPPORTED;
                return 0;
@@ -2087,7 +2088,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
                      gc_ver == IP_VERSION(11, 0, 2) ||
                      gc_ver == IP_VERSION(11, 0, 3) ||
                      gc_ver == IP_VERSION(9, 4, 3) ||
-                     gc_ver == IP_VERSION(9, 4, 4)))
+                     gc_ver == IP_VERSION(9, 4, 4) ||
+                     gc_ver == IP_VERSION(9, 5, 0)))
                        *states = ATTR_STATE_UNSUPPORTED;
        } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
                if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2109,7 +2111,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
                      gc_ver == IP_VERSION(11, 0, 2) ||
                      gc_ver == IP_VERSION(11, 0, 3) ||
                      gc_ver == IP_VERSION(9, 4, 3) ||
-                     gc_ver == IP_VERSION(9, 4, 4)))
+                     gc_ver == IP_VERSION(9, 4, 4) ||
+                     gc_ver == IP_VERSION(9, 5, 0)))
                        *states = ATTR_STATE_UNSUPPORTED;
        } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
                if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2120,7 +2123,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
        } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
                if (gc_ver == IP_VERSION(9, 4, 2) ||
                    gc_ver == IP_VERSION(9, 4, 3) ||
-                   gc_ver == IP_VERSION(9, 4, 4))
+                   gc_ver == IP_VERSION(9, 4, 4) ||
+                   gc_ver == IP_VERSION(9, 5, 0))
                        *states = ATTR_STATE_UNSUPPORTED;
        }

@@ -2416,6 +2420,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
                case IP_VERSION(9, 4, 2):
                case IP_VERSION(9, 4, 3):
                case IP_VERSION(9, 4, 4):
+               case IP_VERSION(9, 5, 0):
                case IP_VERSION(10, 3, 0):
                case IP_VERSION(11, 0, 0):
                case IP_VERSION(11, 0, 1):
@@ -3530,7 +3535,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,

        /* Skip crit temp on APU */
        if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
-           (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4))) &&
+           (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4) ||
+            gc_ver == IP_VERSION(9, 5, 0))) &&
            (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
             attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
                return 0;
@@ -3605,7 +3611,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
        if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
             adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
             (gc_ver == IP_VERSION(9, 4, 3) ||
-             gc_ver == IP_VERSION(9, 4, 4))) &&
+             gc_ver == IP_VERSION(9, 4, 4) ||
+             gc_ver == IP_VERSION(9, 5, 0))) &&
            (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
             attr == &sensor_dev_attr_in0_label.dev_attr.attr))
                return 0;
@@ -3613,7 +3620,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
        /* only APUs other than gc 9,4,3 have vddnb */
        if ((!(adev->flags & AMD_IS_APU) ||
             (gc_ver == IP_VERSION(9, 4, 3) ||
-             gc_ver == IP_VERSION(9, 4, 4))) &&
+             gc_ver == IP_VERSION(9, 4, 4) ||
+             gc_ver == IP_VERSION(9, 5, 0))) &&
            (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
             attr == &sensor_dev_attr_in1_label.dev_attr.attr))
                return 0;
@@ -3636,7 +3644,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,

        /* hotspot temperature for gc 9,4,3*/
        if (gc_ver == IP_VERSION(9, 4, 3) ||
-           gc_ver == IP_VERSION(9, 4, 4)) {
+           gc_ver == IP_VERSION(9, 4, 4) ||
+           gc_ver == IP_VERSION(9, 5, 0)) {
                if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
                    attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
                    attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
--
2.46.0