[PATCH] drm/amd/display: restore invalid MSA timing check for freesync

[Harry Wentland]

On 2025-01-27 19:41, Melissa Wen wrote:
> This restores the original behavior that gets min/max freq from EDID and
> only set DP/eDP connector as freesync capable if "sink device is capable
> of rendering incoming video stream without MSA timing parameters", i.e.,
> `allow_invalid_MSA_timing_params` is true. The condition was mistakenly
> removed by 0159f88a99c9 ("drm/amd/display: remove redundant freesync
> parser for DP").
> 
> CC: Mario Limonciello <mario.limonciello at amd.com>
> CC: Alex Hung <alex.hung at amd.com>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3915
> Fixes: 0159f88a99c9 ("drm/amd/display: remove redundant freesync parser for DP")
> Signed-off-by: Melissa Wen <mwen at igalia.com>

Yeah, we need to check IGNORE_MSA_TIMING_PARAM before
allowing Freesync / adaptive sync.

Thanks for the fix.

Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Harry

> ---
> 
> 
> Mario, Alex,
> 
> I can't reproduce the reported issue on my side, but reporters mentioned
> this fixes their black screen issue. I examined the code around it and
> overall restoring this condition in this way seems right.
> 
> For the future, we can consider using
> `drm_dp_sink_can_do_video_without_timing_msa` instead.
> 
> Anyway, from my tests, what I can say is that things seem stable and I
> didn't noticed any changes.
> 
> Can you verify how it goes on the CI?
> 
> Thanks,
> 
> Melissa 
> 
> 
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index c9e8982a8804..da550a257f09 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -12381,10 +12381,14 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
>  
>  	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
>  		     sink->sink_signal == SIGNAL_TYPE_EDP)) {
> -		amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
> -		amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
> -		if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
> -			freesync_capable = true;
> +		if (amdgpu_dm_connector->dc_link &&
> +		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
> +			amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
> +			amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
> +			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
> +				freesync_capable = true;
> +		}
> +
>  		parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
>  
>  		if (vsdb_info.replay_mode) {