[PATCH v3 10/10] drm/amdgpu: Enable devcoredump for JPEG5_0_0

[Sundararaju, Sathishkumar]

Hi Leo, Thank you.

Regards,
Sathish

On 1/30/2025 7:18 PM, Liu, Leo wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Reviewed-by: Leo Liu <leo.liu at amd.com>
>
>> -----Original Message-----
>> From: Sundararaju, Sathishkumar <Sathishkumar.Sundararaju at amd.com>
>> Sent: January 30, 2025 4:51 AM
>> To: amd-gfx at lists.freedesktop.org
>> Cc: Liu, Leo <Leo.Liu at amd.com>; Lazar, Lijo <Lijo.Lazar at amd.com>;
>> Sundararaju, Sathishkumar <Sathishkumar.Sundararaju at amd.com>
>> Subject: [PATCH v3 10/10] drm/amdgpu: Enable devcoredump for JPEG5_0_0
>>
>> Add register list and enable devcoredump for JPEG5_0_0
>>
>> V2: (Lijo)
>>   - remove version specific callbacks and use simplified helper functions
>>
>> V3: (Lijo)
>>   - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
>>
>> Signed-off-by: Sathishkumar S <sathishkumar.sundararaju at amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 22
>> ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> index d5cf0f2799d4..4a55e0cf39e4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> @@ -34,6 +34,22 @@
>>   #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"
>>   #include "jpeg_v5_0_0.h"
>>
>> +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0[] = {
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0,
>> regJPEG_DEC_GFX10_ADDR_CONFIG),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0,
>> regJPEG_DEC_Y_GFX10_TILING_SURFACE),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0,
>> regJPEG_DEC_UV_GFX10_TILING_SURFACE),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
>> +     SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), };
>> +
>>   static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);  static
>> int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> @@ -100,6 +116,10 @@ static int jpeg_v5_0_0_sw_init(struct
>> amdgpu_ip_block *ip_block)
>>        adev->jpeg.internal.jpeg_pitch[0] =
>> regUVD_JPEG_PITCH_INTERNAL_OFFSET;
>>        adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG,
>> 0, regUVD_JPEG_PITCH);
>>
>> +     r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0,
>> ARRAY_SIZE(jpeg_reg_list_5_0));
>> +     if (r)
>> +             return r;
>> +
>>        /* TODO: Add queue reset mask when FW fully supports it */
>>        adev->jpeg.supported_reset =
>>                amdgpu_get_soft_full_reset_mask(&adev-
>>> jpeg.inst[0].ring_dec[0]);
>> @@ -637,6 +657,8 @@ static const struct amd_ip_funcs
>> jpeg_v5_0_0_ip_funcs = {
>>        .wait_for_idle = jpeg_v5_0_0_wait_for_idle,
>>        .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
>>        .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
>> +     .dump_ip_state = amdgpu_jpeg_dump_ip_state,
>> +     .print_ip_state = amdgpu_jpeg_print_ip_state,
>>   };
>>
>>   static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
>> --
>> 2.25.1