[PATCH 06/33] drm/amdgpu: clean up jpeg reset functions
Sundararaju, Sathishkumar
sathishkumar.sundararaju at amd.com
Mon Jul 14 03:24:19 UTC 2025
This patch is :-
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju at amd.com>
On 7/12/2025 4:09 AM, Alex Deucher wrote:
> Make them consistent and use the reset flags.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 6 +++++-
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 6 +++++-
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 6 +++++-
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 7 ++++---
> 4 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index 5ba1c5ad9a5e1..0b56cb67e8f1d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -118,7 +118,8 @@ static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> + if (!amdgpu_sriov_vf(adev))
> + adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
>
> return r;
> @@ -770,6 +771,9 @@ static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring,
> {
> int r;
>
> + if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
> + return -EOPNOTSUPP;
> +
> drm_sched_wqueue_stop(&ring->sched);
> r = jpeg_v2_0_stop(ring->adev);
> if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> index 5be9cdcae32c1..3d0e61f9f2854 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> @@ -167,7 +167,8 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> + if (!amdgpu_sriov_vf(adev))
> + adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
>
> return r;
> @@ -649,6 +650,9 @@ static int jpeg_v2_5_ring_reset(struct amdgpu_ring *ring,
> {
> int r;
>
> + if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
> + return -EOPNOTSUPP;
> +
> drm_sched_wqueue_stop(&ring->sched);
> jpeg_v2_5_stop_inst(ring->adev, ring->me);
> jpeg_v2_5_start_inst(ring->adev, ring->me);
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index 5428930eafa3e..5d54c882d889c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -132,7 +132,8 @@ static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> + if (!amdgpu_sriov_vf(adev))
> + adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
>
> return r;
> @@ -561,6 +562,9 @@ static int jpeg_v3_0_ring_reset(struct amdgpu_ring *ring,
> {
> int r;
>
> + if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
> + return -EOPNOTSUPP;
> +
> drm_sched_wqueue_stop(&ring->sched);
> r = jpeg_v3_0_stop(ring->adev);
> if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index 78fe1924f3cb7..5485e983a089f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -143,7 +143,8 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> + if (!amdgpu_sriov_vf(adev))
> + adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
> r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
>
> return r;
> @@ -726,8 +727,8 @@ static int jpeg_v4_0_ring_reset(struct amdgpu_ring *ring,
> {
> int r;
>
> - if (amdgpu_sriov_vf(ring->adev))
> - return -EINVAL;
> + if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
> + return -EOPNOTSUPP;
>
> drm_sched_wqueue_stop(&ring->sched);
> r = jpeg_v4_0_stop(ring->adev);
More information about the amd-gfx
mailing list