[PATCH 3/3] drm/amdgpu/gfx12: set MQD as appriopriate for queue types

[Liang, Prike]

[Public]

What if when the kernel queue and user queue are enabled at the same time,
then how to handle the case when userq mapped to a queue that has been
enabled privileged bit by kernel queue?

Regards,
      Prike

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Lazar, Lijo
> Sent: Friday, July 18, 2025 12:13 PM
> To: Deucher, Alexander <Alexander.Deucher at amd.com>; amd-
> gfx at lists.freedesktop.org
> Cc: Koenig, Christian <Christian.Koenig at amd.com>
> Subject: Re: [PATCH 3/3] drm/amdgpu/gfx12: set MQD as appriopriate for queue
> types
>
>
>
> On 7/17/2025 3:31 AM, Alex Deucher wrote:
> > Set the MQD as appropriate for the kernel vs user queues.
> >
> > Acked-by: Christian König <christian.koenig at amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>
> A couple of nit-picks for patch 1.
>
> Series is -
>
>       Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>
>
> Thanks,
> Lijo
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > index 7220ed2fa2a33..73a04d07bb494 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > @@ -3020,6 +3020,8 @@ static int gfx_v12_0_gfx_mqd_init(struct
> > amdgpu_device *adev, void *m,  #endif
> >     if (prop->tmz_queue)
> >             tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH,
> 1);
> > +   if (!prop->kernel_queue)
> > +           tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL,
> RB_NON_PRIV, 1);
> >     mqd->cp_gfx_hqd_cntl = tmp;
> >
> >     /* set up cp_doorbell_control */
> > @@ -3169,8 +3171,10 @@ static int gfx_v12_0_compute_mqd_init(struct
> amdgpu_device *adev, void *m,
> >                         (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
> >     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL,
> UNORD_DISPATCH, 1);
> >     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL,
> TUNNEL_DISPATCH, 0);
> > -   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
> > -   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
> > +   if (prop->kernel_queue) {
> > +           tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL,
> PRIV_STATE, 1);
> > +           tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL,
> KMD_QUEUE, 1);
> > +   }
> >     if (prop->tmz_queue)
> >             tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
> >     mqd->cp_hqd_pq_control = tmp;