[PATCH 1/3] drm/amd/display: Fix refactored DSC cap calculation

[Timur Kristóf]

After refactoring the DSC capability calculation, the
get_min_slice_count_for_odm could crash on some GPUs due to a
division by zero when max_total_throughput_mps was zero.
As a result, DC was broken when connecting a GPU that doesn't
support DSC to a monitor that supports DSC.
Tested on Oland (DCE 6) and Fiji (DCE 10).

This commit fixes it by returning zero instead.

Fixes: 4909b8b3846c ("drm/amd/display: Refactor DSC cap calculations")
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
---
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index a454d16e6586..4169ece9c535 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -642,14 +642,15 @@ static unsigned int get_min_slice_count_for_odm(
 	unsigned int max_dispclk_khz;
 
 	/* get max pixel rate and combine caps */
-	max_dispclk_khz = dsc_enc_caps->max_total_throughput_mps * 1000;
-	if (dsc && dsc->ctx->dc) {
-		if (dsc->ctx->dc->clk_mgr &&
-			dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {
-			/* dispclk is available */
-			max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);
-		}
-	}
+	if (dsc && dsc->ctx->dc && dsc->ctx->dc->clk_mgr &&
+		dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz)
+		max_dispclk_khz =
+			dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(
+				dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);
+	else if (dsc_enc_caps->max_total_throughput_mps)
+		max_dispclk_khz = dsc_enc_caps->max_total_throughput_mps * 1000;
+	else
+		return 0;
 
 	/* consider minimum odm slices required due to
 	 * 1) display pipe throughput (dispclk)
-- 
2.50.1