[PATCH 02/28] drm/amdgpu/gfx7: drop reset_kgq

[Alex Deucher]

On Mon, Jun 2, 2025 at 8:57 AM Christian König <christian.koenig at amd.com> wrote:
>
> On 5/29/25 22:07, Alex Deucher wrote:
> > It doesn't work reliably and we have soft recover and
> > full adapter reset so drop this.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>
> I was really hoping that this would be more reliable than soft recovery at some point. And from my testing on gfx9 it seems to work rather reliable.
>
> Are you sure we should just drop that?

I couldn't get it to work reliably at all on any of the gfx8 or 9
hardware I tried.  We can always revert the patches if anyone wants to
work on it again.

Alex

>
> Regards,
> Christian.
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 71 ---------------------------
> >  1 file changed, 71 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > index da0534ff1271a..2aa323dab34e3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> > @@ -4884,76 +4884,6 @@ static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
> >       amdgpu_ring_write(ring, 0x0000000A);    /* poll interval */
> >  }
> >
> > -static void gfx_v7_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
> > -                               int mem_space, int opt, uint32_t addr0,
> > -                               uint32_t addr1, uint32_t ref, uint32_t mask,
> > -                               uint32_t inv)
> > -{
> > -     amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
> > -     amdgpu_ring_write(ring,
> > -                       /* memory (1) or register (0) */
> > -                       (WAIT_REG_MEM_MEM_SPACE(mem_space) |
> > -                        WAIT_REG_MEM_OPERATION(opt) | /* wait */
> > -                        WAIT_REG_MEM_FUNCTION(3) |  /* equal */
> > -                        WAIT_REG_MEM_ENGINE(eng_sel)));
> > -
> > -     if (mem_space)
> > -             BUG_ON(addr0 & 0x3); /* Dword align */
> > -     amdgpu_ring_write(ring, addr0);
> > -     amdgpu_ring_write(ring, addr1);
> > -     amdgpu_ring_write(ring, ref);
> > -     amdgpu_ring_write(ring, mask);
> > -     amdgpu_ring_write(ring, inv); /* poll interval */
> > -}
> > -
> > -static void gfx_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
> > -                                     uint32_t val, uint32_t mask)
> > -{
> > -     gfx_v7_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
> > -}
> > -
> > -static int gfx_v7_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
> > -{
> > -     struct amdgpu_device *adev = ring->adev;
> > -     struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
> > -     struct amdgpu_ring *kiq_ring = &kiq->ring;
> > -     unsigned long flags;
> > -     u32 tmp;
> > -     int r;
> > -
> > -     if (amdgpu_sriov_vf(adev))
> > -             return -EINVAL;
> > -
> > -     if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
> > -             return -EINVAL;
> > -
> > -     spin_lock_irqsave(&kiq->ring_lock, flags);
> > -
> > -     if (amdgpu_ring_alloc(kiq_ring, 5)) {
> > -             spin_unlock_irqrestore(&kiq->ring_lock, flags);
> > -             return -ENOMEM;
> > -     }
> > -
> > -     tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
> > -     gfx_v7_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp);
> > -     amdgpu_ring_commit(kiq_ring);
> > -
> > -     spin_unlock_irqrestore(&kiq->ring_lock, flags);
> > -
> > -     r = amdgpu_ring_test_ring(kiq_ring);
> > -     if (r)
> > -             return r;
> > -
> > -     if (amdgpu_ring_alloc(ring, 7 + 12 + 5))
> > -             return -ENOMEM;
> > -     gfx_v7_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr,
> > -                                  ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC);
> > -     gfx_v7_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);
> > -     gfx_v7_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);
> > -
> > -     return amdgpu_ring_test_ring(ring);
> > -}
> > -
> >  static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
> >       .name = "gfx_v7_0",
> >       .early_init = gfx_v7_0_early_init,
> > @@ -5003,7 +4933,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
> >       .emit_wreg = gfx_v7_0_ring_emit_wreg,
> >       .soft_recovery = gfx_v7_0_ring_soft_recovery,
> >       .emit_mem_sync = gfx_v7_0_emit_mem_sync,
> > -     .reset = gfx_v7_0_reset_kgq,
> >  };
> >
> >  static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
>