[PATCH V9 16/43] drm/colorop: Add 3x4 CTM type

[Ville Syrjälä]

On Tue, Jun 17, 2025 at 05:33:20AM +0000, Borah, Chaitanya Kumar wrote:
> 
> 
> > -----Original Message-----
> > From: Pekka Paalanen <pekka.paalanen at collabora.com>
> > Sent: Monday, June 16, 2025 7:02 PM
> > To: Borah, Chaitanya Kumar <chaitanya.kumar.borah at intel.com>
> > Cc: Alex Hung <alex.hung at amd.com>; dri-devel at lists.freedesktop.org; amd-
> > gfx at lists.freedesktop.org; wayland-devel at lists.freedesktop.org;
> > harry.wentland at amd.com; leo.liu at amd.com; ville.syrjala at linux.intel.com;
> > mwen at igalia.com; jadahl at redhat.com; sebastian.wick at redhat.com;
> > shashank.sharma at amd.com; agoins at nvidia.com; joshua at froggi.es;
> > mdaenzer at redhat.com; aleixpol at kde.org; xaver.hugl at gmail.com;
> > victoria at system76.com; daniel at ffwll.ch; Shankar, Uma
> > <uma.shankar at intel.com>; quic_naseer at quicinc.com;
> > quic_cbraga at quicinc.com; quic_abhinavk at quicinc.com; marcan at marcan.st;
> > Liviu.Dudau at arm.com; sashamcintosh at google.com;
> > louis.chauvet at bootlin.com; Daniel Stone <daniels at collabora.com>
> > Subject: Re: [PATCH V9 16/43] drm/colorop: Add 3x4 CTM type
> > 
> > On Mon, 16 Jun 2025 11:30:23 +0000
> > "Borah, Chaitanya Kumar" <chaitanya.kumar.borah at intel.com> wrote:
> > 
> > > > -----Original Message-----
> > > > From: Alex Hung <alex.hung at amd.com>
> > > > Sent: Wednesday, April 30, 2025 6:41 AM
> > > > To: dri-devel at lists.freedesktop.org; amd-gfx at lists.freedesktop.org
> > > > Cc: wayland-devel at lists.freedesktop.org; harry.wentland at amd.com;
> > > > alex.hung at amd.com; leo.liu at amd.com; ville.syrjala at linux.intel.com;
> > > > pekka.paalanen at collabora.com; contact at emersion.fr; mwen at igalia.com;
> > > > jadahl at redhat.com; sebastian.wick at redhat.com;
> > > > shashank.sharma at amd.com; agoins at nvidia.com; joshua at froggi.es;
> > > > mdaenzer at redhat.com; aleixpol at kde.org; xaver.hugl at gmail.com;
> > > > victoria at system76.com; daniel at ffwll.ch; Shankar, Uma
> > > > <uma.shankar at intel.com>; quic_naseer at quicinc.com;
> > > > quic_cbraga at quicinc.com; quic_abhinavk at quicinc.com;
> > > > marcan at marcan.st; Liviu.Dudau at arm.com; sashamcintosh at google.com;
> > > > Borah, Chaitanya Kumar <chaitanya.kumar.borah at intel.com>;
> > > > louis.chauvet at bootlin.com; Daniel Stone <daniels at collabora.com>
> > > > Subject: [PATCH V9 16/43] drm/colorop: Add 3x4 CTM type
> > > >
> > > > From: Harry Wentland <harry.wentland at amd.com>
> > > >
> > > > This type is used to support a 3x4 matrix in colorops. A 3x4 matrix
> > > > uses the last column as a "bias" column. Some HW exposes support for
> > > > 3x4. The calculation looks like:
> > > >
> > > >  out   matrix    in
> > > >  |R|   |0  1  2  3 |   | R |
> > > >  |G| = |4  5  6  7 | x | G |
> > > >  |B|   |8  9  10 11|   | B |
> > > >                        |1.0|
> > > >
> > > > This is also the first colorop where we need a blob property to
> > > > program the property. For that we'll introduce a new DATA property
> > > > that can be used by all colorop TYPEs requiring a blob. The way a
> > > > DATA blob is read depends on the TYPE of the colorop.
> > > >
> > > > We only create the DATA property for property types that need it.
> > >
> > > Is there any value to adding pre-offsets [1] in the uapi?
> > >
> > >  |R/Cr|    | c0 c1 c2 |   ( |R/Cr|   |preoff0| )   |postoff0|
> > >  |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
> > >  |B/Cb|   | c6 c7 c8 |   ( |B/Cb|   |preoff2| )   |postoff2|
> > >
> > > Handling limited range values is one use case that I can think of.
> > 
> > Hi,
> > 
> > in the mathematical sense, no. A pre-offset can always be converted into a
> > post-offset by multiplying it with the 3x3 matrix (and adding to the existing
> > post-offset). This can be pre-computed, no need to do it separately for every
> > pixel.
> > 
> > For hardware reasons, I have no idea.
> 
> Thank you for the reply, Pekka. Our hardware does allow programming Pre-offsets separately.
> Currently I can't think of a particular advantage of that if mathematically a post-offset does the job but I will keep this thread posted if I find something out.

Just FYI we have three different kinds of hardware:
- 3x3 matrix
- 3x3 matrix + programmable pre offsets + hardcoded post offsets for limited range conversion
- 3x3 matrix + programmable pre and post offsets

-- 
Ville Syrjälä
Intel