[PATCH 1/2] drm/amdgpu: Add user queue instance count reporting for gfx12

[Jesse Zhang]

This change exposes the number of available user queue instances
through the HW IP info query interface. The information helps
user mode drivers properly allocate and manage queue resources.

Key changes:
1. Added userq_gfx_instances and userq_compute_instances fields
   to amdgpu_gfx structure
2. Initialized the values during GFX IP early init for v12
   (only when user queues are not disabled via disable_uq)
3. Exposed the values through drm_amdgpu_info_hw_ip structure
   via amdgpu_hw_ip_info()

The values represent:
- userq_gfx_instances: Number of GFX ring instances available
- userq_compute_instances: Number of compute ring instances available

Signed-off-by: Jesse Zhang <Jesse.Zhang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++++
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c  | 5 +++++
 include/uapi/drm/amdgpu_drm.h           | 2 ++
 4 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 08f268dab8f5..63a7f0e0db5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -452,6 +452,8 @@ struct amdgpu_gfx {
 	unsigned			num_gfx_rings;
 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
 	unsigned			num_compute_rings;
+	unsigned			userq_gfx_instances;
+	unsigned			userq_compute_instances;
 	struct amdgpu_irq_src		eop_irq;
 	struct amdgpu_irq_src		priv_reg_irq;
 	struct amdgpu_irq_src		priv_inst_irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 195ed81d39ff..ff05c82a3dff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -411,6 +411,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 			if (adev->gfx.gfx_ring[i].sched.ready &&
 			    !adev->gfx.gfx_ring[i].no_user_submission)
 				++num_rings;
+
+		result->userq_num_instance = adev->gfx.userq_gfx_instances;
 		ib_start_alignment = 32;
 		ib_size_alignment = 32;
 		break;
@@ -420,6 +422,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 			if (adev->gfx.compute_ring[i].sched.ready &&
 			    !adev->gfx.compute_ring[i].no_user_submission)
 				++num_rings;
+
+		result->userq_num_instance = adev->gfx.userq_compute_instances;
 		ib_start_alignment = 32;
 		ib_size_alignment = 32;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 1234c8d64e20..482490783a0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3852,6 +3852,11 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
 						  AMDGPU_MAX_COMPUTE_RINGS);
 	}
 
+	if (!adev->gfx.disable_uq) {
+		adev->gfx.userq_gfx_instances = GFX12_NUM_GFX_RINGS;
+		adev->gfx.userq_compute_instances = AMDGPU_MAX_COMPUTE_RINGS;
+	}
+
 	gfx_v12_0_set_kiq_pm4_funcs(adev);
 	gfx_v12_0_set_ring_funcs(adev);
 	gfx_v12_0_set_irq_funcs(adev);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 45c4fa13499c..8082270a7ceb 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1493,6 +1493,8 @@ struct drm_amdgpu_info_hw_ip {
 	__u32  available_rings;
 	/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
 	__u32  ip_discovery_version;
+	/* Userq available instance */
+	__u32  userq_num_instance;
 };
 
 /* GFX metadata BO sizes and alignment info (in bytes) */
-- 
2.34.1