[PATCH 2/2] drm/amdgpu: fix the gb_addr_config_fields init value mismatch

[Zhang, Morris]

[AMD Official Use Only - AMD Internal Distribution Only]


Thanks @Lazar, Lijo<mailto:Lijo.Lazar at amd.com> for the review.

And initializing the gb_addr_config_fields is part of sw_init although the callback has the name of early_init in it.

Will remove the part of " Fix it temporarily by using the golden value in sw_init as well."  in comment.



> -----Original Message-----

> From: Lazar, Lijo <Lijo.Lazar at amd.com>

> Sent: Wednesday, March 5, 2025 4:02 PM

> To: Zhang, Morris <Shiwu.Zhang at amd.com>; Ma, Le <Le.Ma at amd.com>; Zhang,

> Hawking <Hawking.Zhang at amd.com>; amd-gfx at lists.freedesktop.org

> Subject: Re: [PATCH 2/2] drm/amdgpu: fix the gb_addr_config_fields init value

> mismatch

>

>

>

> On 3/5/2025 12:14 PM, Shiwu Zhang wrote:

> > For gfx_v9_4_3 specifically, before regGB_ADDR_CONFIG is overwritten

> > in gfx hw_init it is read out to popluate the gb_addr_config_fields in

> > the sw_init stage, which causes mismatch.

> >

> > Fix it temporarily by using the golden value in sw_init as well.

>

> sw_init => early_init

>

> > The final fix should be by vBIOS/IFWI.

>

> This is supposed to be a driver-set golden reg. Most likely will remain this way.

>

> Series is -

>

>          Reviewed-by: Lijo Lazar <lijo.lazar at amd.com<mailto:lijo.lazar at amd.com>>

>

> Thanks,

> Lijo

>

> >

> > Signed-off-by: Shiwu Zhang <shiwu.zhang at amd.com<mailto:shiwu.zhang at amd.com>>

> > ---

> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 +-----

> >  1 file changed, 1 insertion(+), 5 deletions(-)

> >

> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

> > index 2705f0cdd6da..af9b784eb78d 100644

> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

> > @@ -918,8 +918,6 @@ static const struct aca_info gfx_v9_4_3_aca_info =

> > {

> >

> >  static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)  {

> > -    u32 gb_addr_config;

> > -

> >       adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;

> >       adev->gfx.ras = &gfx_v9_4_3_ras;

> >

> > @@ -928,9 +926,7 @@ static int gfx_v9_4_3_gpu_early_init(struct

> amdgpu_device *adev)

> >       adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

> >       adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

> >       adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

> > -    gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0),

> regGB_ADDR_CONFIG);

> > -

> > -    adev->gfx.config.gb_addr_config = gb_addr_config;

> > +   adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG;

> >

> >       adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

> >                               REG_GET_FIELD(


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