[PATCH 08/11] drm/amdgpu/gfx12: add support for disable_kq
Khatri, Sunil
sukhatri at amd.com
Fri Mar 14 11:43:14 UTC 2025
Reviewed-by: Sunil Khatri <sunil.khatri at amd.com>
On 3/13/2025 8:11 PM, Alex Deucher wrote:
> Plumb in support for disabling kernel queues.
>
> v2: use ring counts per Felix' suggestion
> v3: fix stream fault handler, enable EOP interrupts
> v4: fix MEC interrupt offset (Sunil)
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 183 +++++++++++++++++--------
> 1 file changed, 125 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 34cf187e72d9f..a99507e4fdb27 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -1421,11 +1421,13 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
> break;
> }
>
> - /* recalculate compute rings to use based on hardware configuration */
> - num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
> - adev->gfx.mec.num_queue_per_pipe) / 2;
> - adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
> - num_compute_rings);
> + if (adev->gfx.num_compute_rings) {
> + /* recalculate compute rings to use based on hardware configuration */
> + num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
> + adev->gfx.mec.num_queue_per_pipe) / 2;
> + adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
> + num_compute_rings);
> + }
>
> /* EOP Event */
> r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
> @@ -1471,37 +1473,41 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
> return r;
> }
>
> - /* set up the gfx ring */
> - for (i = 0; i < adev->gfx.me.num_me; i++) {
> - for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
> - for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
> - if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
> - continue;
> -
> - r = gfx_v12_0_gfx_ring_init(adev, ring_id,
> - i, k, j);
> - if (r)
> - return r;
> - ring_id++;
> + if (adev->gfx.num_gfx_rings) {
> + /* set up the gfx ring */
> + for (i = 0; i < adev->gfx.me.num_me; i++) {
> + for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
> + for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
> + if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
> + continue;
> +
> + r = gfx_v12_0_gfx_ring_init(adev, ring_id,
> + i, k, j);
> + if (r)
> + return r;
> + ring_id++;
> + }
> }
> }
> }
>
> - ring_id = 0;
> - /* set up the compute queues - allocate horizontally across pipes */
> - for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
> - for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
> - for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
> - if (!amdgpu_gfx_is_mec_queue_enabled(adev,
> - 0, i, k, j))
> - continue;
> + if (adev->gfx.num_compute_rings) {
> + ring_id = 0;
> + /* set up the compute queues - allocate horizontally across pipes */
> + for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
> + for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
> + for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
> + if (!amdgpu_gfx_is_mec_queue_enabled(adev,
> + 0, i, k, j))
> + continue;
>
> - r = gfx_v12_0_compute_ring_init(adev, ring_id,
> - i, k, j);
> - if (r)
> - return r;
> + r = gfx_v12_0_compute_ring_init(adev, ring_id,
> + i, k, j);
> + if (r)
> + return r;
>
> - ring_id++;
> + ring_id++;
> + }
> }
> }
> }
> @@ -3495,12 +3501,18 @@ static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
> if (r)
> return r;
>
> - if (!amdgpu_async_gfx_ring) {
> - r = gfx_v12_0_cp_gfx_resume(adev);
> - if (r)
> - return r;
> + if (adev->gfx.num_gfx_rings) {
> + if (!amdgpu_async_gfx_ring) {
> + r = gfx_v12_0_cp_gfx_resume(adev);
> + if (r)
> + return r;
> + } else {
> + r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
> + if (r)
> + return r;
> + }
> } else {
> - r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
> + r = gfx_v12_0_cp_gfx_start(adev);
> if (r)
> return r;
> }
> @@ -3711,6 +3723,46 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
> return r;
> }
>
> +static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
> + bool enable)
> +{
> + if (adev->gfx.disable_kq) {
> + unsigned int irq_type;
> + int m, p, r;
> +
> + for (m = 0; m < adev->gfx.me.num_me; m++) {
> + for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
> + irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
> + if (enable)
> + r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
> + irq_type);
> + else
> + r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
> + irq_type);
> + if (r)
> + return r;
> + }
> + }
> +
> + for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
> + for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
> + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> + + (m * adev->gfx.mec.num_pipe_per_mec)
> + + p;
> + if (enable)
> + r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
> + irq_type);
> + else
> + r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
> + irq_type);
> + if (r)
> + return r;
> + }
> + }
> + }
> + return 0;
> +}
> +
> static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> @@ -3721,6 +3773,7 @@ static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
> amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
> amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
> amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
> + gfx_v12_0_set_userq_eop_interrupts(adev, false);
>
> if (!adev->no_hw_access) {
> if (amdgpu_async_gfx_ring) {
> @@ -3809,11 +3862,19 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
>
> + if (amdgpu_disable_kq == 1)
> + adev->gfx.disable_kq = true;
> +
> adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
>
> - adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
> - adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
> - AMDGPU_MAX_COMPUTE_RINGS);
> + if (adev->gfx.disable_kq) {
> + adev->gfx.num_gfx_rings = 0;
> + adev->gfx.num_compute_rings = 0;
> + } else {
> + adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
> + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
> + AMDGPU_MAX_COMPUTE_RINGS);
> + }
>
> gfx_v12_0_set_kiq_pm4_funcs(adev);
> gfx_v12_0_set_ring_funcs(adev);
> @@ -3844,6 +3905,10 @@ static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> + r = gfx_v12_0_set_userq_eop_interrupts(adev, true);
> + if (r)
> + return r;
> +
> return 0;
> }
>
> @@ -5043,27 +5108,29 @@ static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
> pipe_id = (entry->ring_id & 0x03) >> 0;
> queue_id = (entry->ring_id & 0x70) >> 4;
>
> - switch (me_id) {
> - case 0:
> - for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> - ring = &adev->gfx.gfx_ring[i];
> - if (ring->me == me_id && ring->pipe == pipe_id &&
> - ring->queue == queue_id)
> - drm_sched_fault(&ring->sched);
> - }
> - break;
> - case 1:
> - case 2:
> - for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> - ring = &adev->gfx.compute_ring[i];
> - if (ring->me == me_id && ring->pipe == pipe_id &&
> - ring->queue == queue_id)
> - drm_sched_fault(&ring->sched);
> + if (!adev->gfx.disable_kq) {
> + switch (me_id) {
> + case 0:
> + for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> + ring = &adev->gfx.gfx_ring[i];
> + if (ring->me == me_id && ring->pipe == pipe_id &&
> + ring->queue == queue_id)
> + drm_sched_fault(&ring->sched);
> + }
> + break;
> + case 1:
> + case 2:
> + for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> + ring = &adev->gfx.compute_ring[i];
> + if (ring->me == me_id && ring->pipe == pipe_id &&
> + ring->queue == queue_id)
> + drm_sched_fault(&ring->sched);
> + }
> + break;
> + default:
> + BUG();
> + break;
> }
> - break;
> - default:
> - BUG();
> - break;
> }
> }
>
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